JPS641368A - Image forming device - Google Patents

Image forming device

Info

Publication number
JPS641368A
JPS641368A JP62155536A JP15553687A JPS641368A JP S641368 A JPS641368 A JP S641368A JP 62155536 A JP62155536 A JP 62155536A JP 15553687 A JP15553687 A JP 15553687A JP S641368 A JPS641368 A JP S641368A
Authority
JP
Japan
Prior art keywords
logical operation
registers
signals
alus
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62155536A
Other languages
Japanese (ja)
Other versions
JPH011368A (en
Inventor
Yoshibumi Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP62-155536A priority Critical patent/JPH011368A/en
Priority claimed from JP62-155536A external-priority patent/JPH011368A/en
Publication of JPS641368A publication Critical patent/JPS641368A/en
Publication of JPH011368A publication Critical patent/JPH011368A/en
Pending legal-status Critical Current

Links

Landscapes

  • Editing Of Facsimile Originals (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Image Processing (AREA)

Abstract

PURPOSE:To improve a processing speed by executing image synthesis processing (logical operation) more than two by means of hardware. CONSTITUTION:For generating video signals A and B, a CPU2 starts a direct memory access (DMA). The started DMA loads an address on a bus 300, accesses bit map memories 31a and 31b, and objective data is outputted to a bus between ALUs 35a and 35b. The data is connected with the ALUs 35a and 35b and logical operation is executed in accordance with instruction registers 34a and 34b. The operated results are respectively outputted to registers 36a and 36b as output signals. The outputs of the registers 36a and 36b are inputted to video signal generation circuits 37a and 37b, and are synchronized with video clock signals, whereby the video signals A and B are generated. Since the image synthesis (logical operation) processings >=2 times are executed by hardware, the processing speed can be improved.
JP62-155536A 1987-06-24 image forming device Pending JPH011368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-155536A JPH011368A (en) 1987-06-24 image forming device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-155536A JPH011368A (en) 1987-06-24 image forming device

Publications (2)

Publication Number Publication Date
JPS641368A true JPS641368A (en) 1989-01-05
JPH011368A JPH011368A (en) 1989-01-05

Family

ID=

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03223935A (en) * 1990-01-29 1991-10-02 Mitsubishi Electric Corp Arithmetic processing semiconductor device
US9801312B2 (en) 2013-05-31 2017-10-24 Fujitsu Limited Data center with air flow control

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03223935A (en) * 1990-01-29 1991-10-02 Mitsubishi Electric Corp Arithmetic processing semiconductor device
US9801312B2 (en) 2013-05-31 2017-10-24 Fujitsu Limited Data center with air flow control

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