JPS6417460A - Semiconductor logic integrated circuit device - Google Patents

Semiconductor logic integrated circuit device

Info

Publication number
JPS6417460A
JPS6417460A JP17336287A JP17336287A JPS6417460A JP S6417460 A JPS6417460 A JP S6417460A JP 17336287 A JP17336287 A JP 17336287A JP 17336287 A JP17336287 A JP 17336287A JP S6417460 A JPS6417460 A JP S6417460A
Authority
JP
Japan
Prior art keywords
input
test
block
terminals
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17336287A
Other languages
Japanese (ja)
Inventor
Masakazu Kaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17336287A priority Critical patent/JPS6417460A/en
Publication of JPS6417460A publication Critical patent/JPS6417460A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To test a small number of outer terminals by providing a shift register for holding input/output data for a test at each functional block, and inputting/ outputting to or from an LSI by a serial transmission through the register. CONSTITUTION:An LSI 100 has a functional block 1 which is not connected directly to an outer input terminal 2 or an outer output terminal 3. A switching unit 5 is so operated at a normal time that a signal from other logic circuit 4 is input to the block 1. The outputs of first or second flip-flop groups 6 or 7 are input through a selector 8 and the unit 5 to the block 1 at the time of testing, and its output is written in third or fourth flip-flop group 10 or 11. Signals are transmitted through a serial transmission on the basis of the signal from a control signal generator 14 between FF groups 6, 7, 10, 11 and test data terminals 9, 13. Then, a small number of outer terminals are merely used to set an arbitrary test pattern.
JP17336287A 1987-07-11 1987-07-11 Semiconductor logic integrated circuit device Pending JPS6417460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17336287A JPS6417460A (en) 1987-07-11 1987-07-11 Semiconductor logic integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17336287A JPS6417460A (en) 1987-07-11 1987-07-11 Semiconductor logic integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6417460A true JPS6417460A (en) 1989-01-20

Family

ID=15958996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17336287A Pending JPS6417460A (en) 1987-07-11 1987-07-11 Semiconductor logic integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6417460A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009002917A (en) * 2007-06-25 2009-01-08 Ngk Spark Plug Co Ltd Gas sensor and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009002917A (en) * 2007-06-25 2009-01-08 Ngk Spark Plug Co Ltd Gas sensor and manufacturing method thereof

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