JPS6417475A - Manufacture of mos semiconductor device - Google Patents

Manufacture of mos semiconductor device

Info

Publication number
JPS6417475A
JPS6417475A JP17352987A JP17352987A JPS6417475A JP S6417475 A JPS6417475 A JP S6417475A JP 17352987 A JP17352987 A JP 17352987A JP 17352987 A JP17352987 A JP 17352987A JP S6417475 A JPS6417475 A JP S6417475A
Authority
JP
Japan
Prior art keywords
electrode
substrate
regions
lower gate
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17352987A
Other languages
Japanese (ja)
Inventor
Hisao Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP17352987A priority Critical patent/JPS6417475A/en
Publication of JPS6417475A publication Critical patent/JPS6417475A/en
Pending legal-status Critical Current

Links

Landscapes

  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To form a lower gate electrode which is not overlapped with the source and drain between insulating regions by forming the insulating regions with an upper gate electrodes as a mask on the surface of a substrate in a double-side gate type MOSFET. CONSTITUTION:A lower gate insulating film 2, a source region 9, a drain layer 10, a channel layer 11, an upper insulating film 4 and an upper gate electrode 5 are formed on a substrate 1. Then, with the electrode 5 as a mask a semiconductor high resistance substance is doped on the substrate 1 to form an insulator region 7 on the substrate 1. A lower gate electrode 8 which is completely aligned to the electrode 5 is formed between the insulator regions. When it is constructed in this manner, the overlapping capacities of the electrode 8, the regions 9, 10 can be reduced.
JP17352987A 1987-07-11 1987-07-11 Manufacture of mos semiconductor device Pending JPS6417475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17352987A JPS6417475A (en) 1987-07-11 1987-07-11 Manufacture of mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17352987A JPS6417475A (en) 1987-07-11 1987-07-11 Manufacture of mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS6417475A true JPS6417475A (en) 1989-01-20

Family

ID=15962219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17352987A Pending JPS6417475A (en) 1987-07-11 1987-07-11 Manufacture of mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS6417475A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061647A (en) * 1990-10-12 1991-10-29 Motorola, Inc. ITLDD transistor having variable work function and method for fabricating the same
JPH04297348A (en) * 1991-03-26 1992-10-21 Nissan Shatai Co Ltd Peripheral edge sealing structure for vehicle body opening part

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061647A (en) * 1990-10-12 1991-10-29 Motorola, Inc. ITLDD transistor having variable work function and method for fabricating the same
JPH04297348A (en) * 1991-03-26 1992-10-21 Nissan Shatai Co Ltd Peripheral edge sealing structure for vehicle body opening part

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