JPS641803B2 - - Google Patents

Description

Claim 1: an actual value generator, a set value memory device for a set value proportional to the desired running speed, a device for comparing the actual value with the set value, and a device for comparing the actual value with the set value; A device is provided for controlling the vehicle speed and acting on a component for controlling the vehicle speed, the actual value being transferred to the setpoint memory device when the at least one switch device is actuated. In the control device, an auxiliary set value memory device 41 generates a ramp by performing digital counting, and a comparator device to which the ramp value from the auxiliary set value memory device 41 and the set value from the set value memory device 46 are supplied. 112 is provided, and the comparison device 112
is connected on the output side with the setpoint memory device 46, in which case an additional setpoint is provided by means of a ramp value during a change in vehicle speed by the control device, and the setpoint value is When the first switch device 14 is operated with the set value stored in the memory device 46, the instantaneous actual value at that time is transferred to the auxiliary set value memory device 41, and the comparison device 112 stores the additional set value. emit a signal corresponding to the deviation between the ramp value used as the auxiliary setpoint memory device 41 and the setpoint value of the auxiliary setpoint memory device 41, whereby the value transferred to said auxiliary setpoint memory device 41 corresponds to the setting in which it was stored. A digital control device for the vehicle running speed, characterized in that it is varied by means of a ramp until it corresponds to a value, the slope of the ramp decreasing continuously.

2 When the further switch device 15 or 16 is actuated in order to start the acceleration process, the substantially instantaneous actual value is transmitted to the auxiliary setpoint memory device 41, and this transmitted value is transferred by means of a lamp to the further switch device 15. 2. The device as claimed in claim 1, wherein the actual value is changed in accordance with the length of the operating time from 1 to 16 and immediately thereafter the actual value is transmitted to the set value memory device.

3 Device 115 for adding the set value to the instantaneous actual value
3. The device as claimed in claim 1, further comprising transmitting the actual value slightly changed in this way to an auxiliary setpoint memory device.

4. Device according to claim 2, in which, after actuation of the further switch device 15 or 16, a relatively small ramp gradient acts with opposite polarity until the actual value corresponds to the set value.

5 Device 11 for determining variable ramp slope
2,121 has a control device (input side A=O of 111,112), by means of which the ramp slope of the further switch 15 or 16 is set to a maximum value during operation. or the device described in paragraph 3.

6. Device according to one of claims 2 to 5, further comprising a switch device 15, 16 for triggering the positive and negative acceleration steps, respectively.

7 In addition, upon actuation of one of the provided switch devices 15, 16, the actual value is transmitted to the setpoint memory device 46, so that during short-term actuation the instantaneous actual value can be transferred to another setpoint. - The device according to any one of claims 2 to 6, wherein the device is set as a traveling speed value.

8. A device 117 for detecting the difference between the ramp value and the actual value is provided, and a limit value detection circuit 122 is provided, which detects a continued change in the ramp value when the maximum permissible value is exceeded. 8. A device according to any one of claims 1 to 7, wherein:

9. Device according to any one of claims 1 to 8, characterized in that the control circuit has a P- and/or an I- and/or a D-type.

10. Device according to claim 1, characterized in that the control device is shut off when the actual value falls below a settable value (Vmin).

11. The device according to any one of claims 1 to 10, wherein the control device is shut off when the difference value obtained by subtracting the actual value from the peak value (maximum setting value) exceeds a settable value.

12 Claim 1 in which the address control of the values that can be set by the fixed value memory 65 depends on the traveling speed.
The device according to any one of paragraphs 1 to 11.

13. Device according to one of claims 1 to 12, characterized in that the occurrence of a predetermined movement in a vehicle, in particular a brake or clutch movement, causes the control device to be shut off.

14. The device according to any one of claims 1 to 13, wherein the locking state of the adjustment device 100 is released by actuation of one of the switch devices 14, 15, 16.

15 One actual value memory 5 for actual value generator 50
15. Device according to claim 1, characterized in that the actual actual values are continuously stored in the memory.

16 a set value memory device 46 upon actuation of one of the respective switch devices 14, 15, 16 and/or upon the occurrence of an action causing a disconnection of the control device;
16. Device according to claim 1, characterized in that all memory devices except the actual value memory device 52 and preferably the ramp value memory device 41 are reset.

17 Locking devices 170 to 173 are provided which ensure that upon activation of the supply voltage all memory devices are reset and that, depending on the signal of the connection, the memory devices 52, 46, 41 can no longer be reset. 17. A device according to any one of claims 1 to 16.

18 A switching device 114 is provided for switching between the set value memory device 46 and the ramp value memory device 41, in which case the contents of the ramp value memory device 41 are used as the set value for controlling the regulating device 100 as the ramp value. 18. The device according to claim 1, wherein the device transmits through until the set values are equal or while the further switch devices 15-16 are activated.

19. The device according to claim 1, further comprising devices 118, 129 for multiplying the control deviation by a factor dependent on the actual value.

20. A pulse control circuit 100 is provided as an adjustment device, and in the control circuit, the amount of adjustment is changed to a pulse voltage with an impact coefficient depending on the amount of adjustment. equipment.

21 The pulse control circuit 100 has a counting device 151 into which, at the timing of the first clock frequency f ₆ , the added adjustment variable is transmitted in each case as a binary number; 21. The device as claimed in claim ₂₀ , wherein the pulse width of the pulse voltage signal is determined in each case by the counting time.

22 Using the output frequency of the rotational speed generator 47 as a relatively high frequency f ₇ , the adjustment control device 79
22. The device according to claim 21, wherein the control is carried out in each case during the measurement of the frequency _f7 .

23 The adjustment drive device is the control device 116, 125,
156, 158, by means of which the regulating drive 79 is adapted to the currently occurring actual value upon actuation of at least one switching device 14-16. 23. Device according to claim 1, wherein the device is movable into a corresponding position.

24. The device according to claim 1, which is constructed as a microcomputer, in particular a one-chip microcomputer.

State of the Art The invention is based on a control device according to the preamble of the main claim. German Patent Application Publication No.
No. 2,546,529 discloses a control device that suddenly provides a new set value when adjusting a change in traveling speed. Since the driving speed can only react relatively slowly, there is a risk of control oscillations that persist at least for some period of time after the new setpoint has been reached. In order to reduce such transient vibrations, the use of a control device with PD characteristics has been proposed in German patent application No.
It is publicly known from Publication No. 2537415. like this
In PD- or P-control systems, the speed controlled after the setting process is inaccurate due to different loads and inaccuracies in the actuation of the adjusting elements. On the other hand, if an I-control device is used, the ride quality is even worse.

ADVANTAGES OF THE INVENTION The invention has the following advantages due to the features forming the characterizing part of the main claim. By making the transition, the error after each setting becomes zero, and a smooth transition is achieved, thereby making it possible to achieve good riding comfort.
A slow ramp shifts the ramp value until the actual value equals the set value. In that case, the ramp value is fixed as the set value. By that,
All factors influencing the setting process are removed.

An optimal implementation is possible by using a microcomputer, in particular a one-chip computer. In this way, a digital control device can be realized very simply, inexpensively and with a small construction volume.

Drawings The invention will now be described in detail with reference to embodiments with reference to the drawings.

FIG. 1 is a block diagram of a vehicle speed control device for explaining the present invention, FIG. 2 is a diagram for explaining the acceleration process performed by the vehicle speed control device of FIG. 1, and FIG. 3 is a diagram for explaining the vehicle speed in advance. FIG. 4 is a block diagram showing an embodiment of the vehicle speed control device according to the present invention, and FIG. 6 is a diagram illustrating the same process when the road on which the vehicle is traveling is sloped; FIG. 7 is a circuit diagram of the regulating device configured as a pulse control circuit; FIG. 7 is a diagram for explaining the operation of the pulse control circuit shown in FIG. 7, and FIG. 9 is a circuit configuration diagram of the initial value setting device.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows a vehicle speed control device for explaining the present invention. In this device, a positive potential-carrying terminal 10 is connected via a main switch 11 for the operational connection of the voltage supply to five switch devices 12 to 16, in particular designed as key switches. The switches 12, 13 are configured as brake/clutch switches and are closed when the brake or clutch of the motor vehicle to which they are connected is actuated. Both switches 12 and 13 are connected to respective input sides of an OR gate 17, and the output side of the OR gate 17 is connected to another OR gate 1.
8 and to the reset input S of flip-flop 19. Switch 14-1
6 is a command circuit for the control device. The first switch 14 is configured as a restart switch. In other words, when the switch is activated,
The previously memorized setpoint-travel speed is restarted. The second switch 15 is configured as a deceleration switch and the third switch 16 as an acceleration switch, i.e. one of these switches
When activated, deceleration or acceleration is performed. In addition, these switches 15, 16, when activated for a short period of time, serve to memorize and maintain the instantaneous driving speed.

Switches 14-16 are connected to respective input sides of OR gate 20 and three AND gates 21-23, and each switch 14-16 has one
Two AND gates 21 to 23 are correspondingly arranged. The outputs of the three AND gates 21 to 23 are connected via an OR gate 24 to the reset input R of the flip-flop 19 and to a further input of the OR gate 18. The main switch 11 is connected via an inverter 25 to another input side of an OR gate 17 and to another input side of an OR gate 18 , and the output side of the OR gate 18 is connected to a terminal 26 . This terminal 26 is connected in a manner not shown in detail to the reset inputs of all memory devices (eg flip-flops and counters) other than the actual value-set value memory, which will be explained in more detail later.

The output sides of the AND gates 22, 23 are connected via an OR gate 27 to one input side of an OR gate 28, the output side of the OR gate 28 is connected to the set input side of a flip-flop 29, and the other input side of the OR gate 28 is connected. And gate 2 on the side
1 and the set input of another flip-flop 30. The output side of the OR gate 27 includes a delay element 31 that acts on the trailing edge of the signal;
It is connected to the reset input side of the flip-flop 29 via an OR gate 32 connected in series thereto. Further, the output side of the OR gate 27 is connected to one input side of an AND gate 34 via an inverter 33, and the other input side of the AND gate 34 is connected to the output side of the flip-flop 29, and one input side of the AND gate 34 is connected to the output side of the flip-flop 29. The side is connected to the terminal 35 to which the first clock f ₁ is applied.
The output side of the OR gate 27 is 1 of the AND gate 36.
connected to one input side of the AND gate 36
The other input side is connected to a terminal 37 to which the second clock frequency _f2 is applied. The output side of the flip-flop 30 is connected to one input side of an AND gate 38, and the other input side of the AND gate 38 is connected to a terminal 39 to which a third clock frequency _f3 is applied.

The outputs of the AND gates 34, 36, 38 are connected via an OR gate 40 to the clock input C of a digital counter 41 which serves as an auxiliary setpoint memory device. The output of the OR gate 24 is connected to the set input S of the counter 41 via a timing element 42, which is configured, for example, as a monostable switch stage, for the generation of short set pulses. The output side of the AND gate 23 is connected to the count direction input side U/D (up/down) of the counter 41 via an OR gate 43.

The output sides of the AND gates 22, 23 are connected via a NOR gate 44 to the trigger input side of another timer element 45, which timer element 45 is connected to the output side of this timer element 45 and connected to the trigger input side of the digital counter 46. Used for generating set signals. This counter 46 is configured as a set value-memory.

The rotational speed generator 47 is used to generate a frequency proportional to the rotational speed and consists of a rotatable disk 48 connected to a wheel, which disk has a number of ferromagnetic marks 49. This ferromagnetic mark is caused to run past an inductive detector 50 and induces one pulse each time there. The output frequency of the rotational speed generator 47 is converted into a data word, in particular a binary number, in a frequency-value converter 51 and fed to a digital counter 52 . This counter 5
2 is connected as an actual value memory device and continuously stores additional actual values. Frequency-value converters are known from US Pat. No. 3,928,797 and, as in the case of rotational speed generators, various known designs and embodiments can be used.

The count output side of the actual value memory 52 is connected to a terminal device 53.
are connected to the numerical input sides of the following components via: auxiliary set value memory 51, set value memory 4
6. Input B of the first digital comparator 54, input B of the second digital comparator 55, input B of the third digital comparator 56, input A of the fourth digital comparator 57, subtraction stage 58 (preferably addition) ), digital counter 59, control-comparison section 6
0 (usually implemented as a summing stage). The numerical output of the auxiliary setpoint memory device 41 is likewise connected to a control comparator 60 , the output of which is connected via a control stage 61 to a further control comparator 62 . This control stage 61 can have P, I, D characteristics or a combination thereof depending on the desired control characteristics. In the known state of the art mentioned at the beginning, a PD control device is used as a control device for the traveling speed of a car.
This will be explained.

The numerical output of the set value memory device 46 is then connected to the numerical input of the component, i.e. the first
The input side A of the digital comparator 54 is connected to the subtraction stage 58, the input side A of the fifth digital comparator 63, and a fixed value memory (ROM) 64. The output side of this fixed value memory 64 is connected to the control comparison section 62. The counting output side of the counter 59 is connected to the input side B of the fourth digital comparator 57 and the input side B of the fifth digital comparator 63, and is connected to the input side B of the fourth digital comparator 57 and the input side B of the fifth digital comparator 63.
5 to the input A of a third digital comparator 56.

If the value applied to the input side A is greater than the value applied to the value B, one signal is generated.The output side of the comparator 57, 63 is an AND gate 66,
It is connected to the set input S of the counter 59 via an OR gate 68 connected in series therewith. The output side of the OR gate 20 is also connected via a timing element 67 to the input side of an OR gate 68 of the counter 59 .

A numerical value is applied to the numerical input A of the second digital comparator 55 via a terminal arrangement 69, preferably by means of a fixed wiring, which provides a limit value for the minimum vehicle speed Vmin. In this case, if the limit value is below, the control device is switched off. Input side A
If the numerical value applied to the input side B is smaller than the numerical value applied to the input side B, the output sides of the digital comparators 55 and 56, where one signal is generated, are connected to the NOR gate 70.
is connected to another input side of the OR gate 70 via. Furthermore, the second digital comparator 5
The output side of 5 is connected to the respective input sides of AND gates 21-23.

The output of the first digital comparator 54, in which an output signal is generated if the value applied to the input A is greater than the value applied to the input B, is connected to another input of the OR gate 43.
A further output of the comparator 54, which produces an output signal if the input values are equal, is connected to a further input of the OR gate 32. Subtraction stage 5
The numerical input side of 8 is the 6th digital comparator 7
Connected to the numerical input side of 1. Terminal device 72
Comparator 7 can advantageously be connected by fixed wiring via
On the numerical input side B of 1, a numerical value ΔY proportional to the speed difference
is added, and the velocity difference provides the inflection point of the ramp slope during the restart process. The output of the sixth digital comparator 71, from which an output signal is generated when the two initially applied values are equal (A=B), is connected to the reset input R of the flip-flop 30.

The numerical output side of the second adjustment/comparison section 62 is connected to the numerical input side A of the seventh digital comparator 73 and the eighth
It is connected to the numerical input side B of the digital comparator 74. Via terminal 75, a value corresponding to the maximum adjustment variable Smax, which must not be exceeded, is preferably applied to the numerical input of comparator 73 by means of fixed wiring. Via the terminal 76, preferably by fixed wiring, the numerical input side A of the comparator 74 is connected.
A value corresponding to the minimum adjustment variable Smin, which must not fall below, is supplied. If the value applied to the value input A is greater than the value applied to the value B, the outputs of the comparators 73, 74, which generate an output signal, are connected via a NOR gate 77 to another input of the AND gate 36. ing.

Furthermore, the numerical output of the second adjustment-comparison section 62 is
A regulating control circuit 78 is supplied, which circuit has a regulating drive, which can be designed, for example, as a regulating motor or a regulating magnet. This regulating drive can drive a component 80 for controlling the speed of the vehicle, which component is designed as a throttle valve in an intake pipe 81 of an internal combustion engine. Other factors which control the speed of the vehicle are, for example, the ignition point, the position of the control rod of the injection pump in the case of ignition engines or injection engines, or the switching point of the injection valve. Adjustment control circuits with adjustment drives are known from the state of the art mentioned at the outset and are proposed in digital form in DE 27 46 545 A1. A blocking input E for the regulating control circuit or regulating drive is connected to the output of the flip-flop 19.

The three clock frequencies f ₁ to _{f 3} used, which are applied to terminals 35, 37, 39, can advantageously be generated by a clock frequency generator, not shown in detail, in which case the various frequencies can be separated. It can be caused by circumference. The four clock frequencies used need not be different in any case, except for both frequencies for different ramp slope types.

The operation of the device shown in Figure 1 will be explained next in Figures 2 and 3.
This will be explained using the diagram shown in the figure. First of all,
It is assumed that the vehicle is moving at a predetermined speed and the main switch 11 is closed. Assume that the vehicle is accelerated using a control device. For this purpose, acceleration switch 16 is actuated, thereby setting flip-flop 29. At the same time, the flip-flop 19 is set via the OR gate 24, so that the blocking state of the regulating control circuit 78 or regulating drive 79 is released. At the same time, orgate 18
Initialization of the memory device takes place via the terminals 26 and 26, as described above. By means of a short pulse of the timing element 42, the counter 41 is loaded with the actual value--the stored contents of the memory 52 Z52 (Vist). (time t ₁
(henceforth) Due to the actuation of the switch 16, the AND gate 34 is blocked by the 0- signal at the output of the inverter 33 while the signal U16 is present.
The AND gate 36 is opened by its signal U16, and the clock frequency _f2 can reach the clock input C of the counter 41 and is counted up from a value corresponding to the actual value, which is applied by the signal U16 to the output of the OR gate 43. This is because a 1- signal appears at , and this signal causes an up count. In the control/comparison section 60, the upcount causes a change in the set value, which also appears in the control/comparison section 62 as an apparent decrease in the actual value. The resulting adjustment variable causes via the regulation control circuit 78 and the internal combustion engine an increase in the power output and thus an increase in the actual actual value, ie the value in the actual value memory 52. This numerical increase lasts until the switch 16 is opened again or until the switch 16, which is designed as a key, is deactivated at time _t2 . The AND gate 36 then blocks the clock frequency f ₂ and blocks the relatively small clock frequency f _{1 .}
can reach the clock input C of the counter 41 via the AND gate 34, and at the same time the signal at the output of the AND gate 23 causes the signal at the output of the AND gate 23 to be transmitted via the OR gate 43 in the counting direction (the counting direction being the output of the comparator 54). (defined by the signal) is performed. Furthermore, at time t ₂ the signal U
The trailing edge of 16 triggers a timing element 45 via a NOR gate 44, whose short output pulse sets a setpoint memory 46 with the actual value occurring at the respective instant. Now control-
The following setting values are added to the comparison section 62, that is, the value Z46 stored in the setting value memory 46.
(Vsoll) is added to the setpoint value formed by the fixed value memory 64 on the basis of the operating characteristic curve of the control device. The value set in the set value memory 46 then forms an address for the fixed value memory 64. Due to the unavoidable low response sensitivity of the control system, the actual value Z52 (Vist) exceeds the set value Z46 (Vsoll) by a small amount after time _t2 . The return control operation is aided by a ramp falling with clock frequency _f1 . When the memorized set value equals the memorized actual value at time _t3 , comparator 5
A reset signal for the flip-flop 29 is generated at the output A=B of the counter 4, which terminates the counting process in the counter 41.

When the vehicle is moving at the regulated vehicle speed and the brakes or clutches of the vehicle are activated, for example due to a dangerous situation, both switches 12, 13 are activated.
one of them is activated, thereby causing terminal 2
6, the memory device is initialized and the flip-flop 19 is reset. By means of this flip-flop, the regulating control circuit 78 or the regulating drive 79 is returned to the unloaded state, and the vehicle is no longer subject to any control action from the control device. When the restart switch is actuated, three flip-flops are set, which unblocks the regulating drive 79 and simultaneously changes the clock frequency f _{1 .}
and f ₃ are applied to the clock input C of the counter 41. This operation is shown in Figure 3, at time t ₄
It begins at . The counter 41 is the actual value memory 5
2 to the value that appears at that time _t4 . Since the set value applied to the input A of the comparator 54 at that moment is greater than the actual value applied to the input B, a signal is produced at the output ``A>B'', which signal is passed through the OR gate 43 to the counter 41.
A count-up occurs in Z41
(Vsoll′). This count-up continues until the next point in time, i.e. until the magnitude of the difference between the actual value and the set value appearing at the output of the subtraction stage 58 reaches the value ΔV (which is, for example, 3 km/h). . When such conditions are equal, comparator 7
The output of 1 resets flip-flop 30, thereby blocking AND gate 38. From this point in time t ₅ onward, a subsequent counter is carried out in counter 41 simply with frequency f ₁ , which results in a relatively flat ramp slope.
Z41 (Vsoll′) is generated. This relatively flat gradient causes the actual value to slowly approach the set value, and an operating point adjustment takes place. When the actual value reaches the set value at time _t6 , the reset of the flip-flop 29 causes the output of the comparator 54 to
=B''. The counting process in counter 41 is completed.

The aforementioned process also takes place in the opposite direction in a corresponding manner, i.e. when the restart key 14 is actuated at an actual speed above the setpoint-speed, the counting process takes place in the opposite counting direction, which means "A> This is because the condition of "B" is no longer given and a 0 signal is supplied to the counting direction input side U/D of the counter 41 via the comparator 54. The same applies when the control device is used to cause deceleration by operating the deceleration switch 15. In this case too, the part of the first ramp runs with a negative slope in the reversal direction of FIG. becomes less than the set value, so that the output side of the comparator 54 “A>
This is because a 1-counting direction signal is generated for the positive counting direction via B''.

At the moment of deactivation of the keys 16 to 15, the set value and the actual value are equal, so that switching off of the adaptive control process at that moment is prevented by the timing element 31. Otherwise, comparator 54 will reset flip-flop 29 via OR gate 32. As the vehicle accelerates, the two values are no longer equal and an adaptive control process is performed.

When one of the keys 15, 16 is actuated for a short time, a short counting process is carried out in the positive or negative direction in the counter 41, as shown in FIG. 2, but this counting process has almost no effect. This is because when such a slight change in the counting state occurs, the control is immediately performed again as shown in FIG. In practice, for such short-term operations, the instantaneous actual value of the vehicle speed is stored and maintained.

Comparators 73, 74 provide a limit to the adjustment variable in order to prevent the control device from changing the adjustment variable to a value that can no longer be realized by the adjustment control circuit or the adjustment drive. Maximum amount of adjustment that can be applied to comparator 73
If the actual adjustment amount exceeds Smax or falls below the minimum adjustment amount Smin applied to the comparator 75, an output signal is generated from the corresponding comparator 73, 74, which output signal blocks the AND gate 36; In counter 41, the subsequent counting process in the case of acceleration and deceleration is terminated.

In order to prevent malfunctions of the control system at low speeds, in particular in the case of special maneuvers of the vehicle, in the case of reversing or in the case of deactivation of the speed generator, the minimum travel speed is determined by the comparator 55.
Vmin is set, and when it falls below this, AND gates 21 to 23 are always blocked. A continuous reset signal for the flip-flop 19 is generated via the NOR gate 70 and the OR gate 17, so that the regulating drive 79 is blocked.

In the case of control, all processes are controlled via ramps, so the deviation of the set value minus the actual value is small and can be used as a highly accurate function. If the deviation obtained by subtracting the actual value from the set value exceeds a predetermined value, it means that something is wrong, such as a break in the brake or clutch signal line. must be carried out. In this case the controller must automatically shut off. The actual value is continuously added to the counter 59. The setting value is
If the actual value instantaneously occurring in the counter 59 is exceeded, the comparator 63 and the AND gate 6
6, a continuous set signal is generated for the counter 59 (as long as the value stored in the counter 59 is at the same time less than the actual actual value).
This second condition is provided by comparator 57. Therefore, the peak value of the actual value is stored in the counter 59 while the set value exceeds the actual value. If the vehicle travels more slowly under these conditions, the actual value will decrease, but the value stored in the counter 59 will remain the same. A fixed value memory 65 stores a function below which an auxiliary cut-off is to be carried out. The function is as follows.

Za=0.75・Ze+Z ₁₀ (however, Za=output value, Ze=input value, Z ₁₀ = equivalent value for a speed of 10km/h) Therefore, if the actual value is 3/4 of that value, the speed of 10km/h , the 1- signal at the output of the comparator 56 switches to a 0- signal,
This 0- signal resets the flip-flop 19 via the NOR gate 70 and the OR gate 17, shutting off the adjustment drive. By means of a function entered into a fixed memory, the cut-off limit value can be set variably as a function of the speed.

When the main switch 11 is opened, a command to return the adjusting drive unit 79 to the no-load state is issued via the inverter 25 and the OR gate 17.

FIG. 4 shows an embodiment of a vehicle speed control device according to the present invention. The part surrounded by the broken line in Figure 1 is
In FIG. 4, it is shown as one block. This block includes component parts 10-26, 44-57,
65 to 70 are included, but their connection configuration is the same as in FIG. 1, so detailed explanation will not be provided. An important difference between the device of FIG. 4 and the device of FIG. 1 is that the regulation control circuit 78 for the regulation drive 79 is not used. In the adjustment control circuit as shown in FIG. 1, in order to detect the position of the adjustment drive section 79,
Requires a transmitter such as a potentiometer. However, in the apparatus of FIG. 4, since the adjustment drive section 79 is actuated by the pulse control circuit 100, there is no need for position detection or a transmitter therefor.

Terminals 101-103 are AND gates 21-23
connected to the output side of the Terminal 101 is connected to the reset input of flip-flop 104, the output of which is connected via OR gate 100 to the input of AND gate 106. From the output side of the AND gate 106, a counter 4 used as a ramp value memory
A clock signal for one clock input C is sent out. As in the device of FIG.
by (via terminal 107) OR gate 4
3 to the counting direction input side U/D of the counter 41
is controlled. The terminals 101 to 103 are connected via an OR gate 108 to a first dynamic input of a timer 109, the output of which is connected to the set input S of the counter 41 and to the input of an AND gate 110. It is connected. The first trigger input of the timing element 109 can be triggered by the positive pulse edge. Terminal 102 is connected to another inverting input of AND gate 110 and to timing element 109.
is connected to a further dynamic trigger input, which further trigger input is triggerable by a negative signal edge. Terminals 102 and 103 are connected to an instruction input side "A=O" of a digital comparator 112 via an OR gate 111. Output side “A=B” is flip-flop 104
is connected to the set input S of the The output of OR gate 111 is additionally connected to an input of OR gate 113 and to a further input of OR gate 105 . The output of flip-flop 104 is connected via an OR gate 113 to a switching input of a switching device 114, which is preferably constructed as a multiplexer.

The actual value applied to the terminal 53 is connected to the input B of the adder 115, to the numerical input of the digital counter 116, to the numerical input B of the subtracter 117, to the address input of the fixed value memory (ROM), and to the control - and the actual value input side of the comparator 119. The set value applied to the terminal device 120 via the output side of the counter 46 is the numerical input side B of the comparator 112.
is applied to the first numerical input side of the switching device 114. The numerical output side of the counter 41 leading to the ramp value is connected to the numerical input side A of the comparator 112, the numerical input side A of the subtracter 117, and the second input side of the switching device 114.
connected to the input side. Comparator 112
The numerical output side “B-A” is the numerical value-frequency converter 1
21 and the variable output frequency f ₄ of that converter is applied to another input of AND gate 106 . The numerical output side “A-B” of the subtracter 117 is the numerical input side B of the comparator 122.
A fixed binary number ΔY is added to the numerical input side A of the comparator. The output “A>B” is connected to another input of the AND gate 106 .

A fixed binary value ΔX is applied to the numerical input A of the adder 115. The numerical output side "A+B" is supplied to the numerical input side of the counter 41.

Terminal 1 connected to the output side of AND gate 110, terminal 107, and output side of flip-flop 19
23 is connected to the input side of an AND gate 124, and the output side of this AND gate is connected to the counter 11.
6 set input side S and flip-flop 125
is connected to the set input side of the terminal 126
A clock frequency _f5 is supplied to the clock input C of the counter 116 via the counter 116. The overflow output CO (carry out) of the counter 116 is connected to the reset input R of the flip-flop 125, and the output side of this flip-flop is connected to the terminal 12.
7 to the input side of the pulse control circuit 100. An advantageous circuit configuration of such a pulse control circuit 100 will be explained in more detail in conjunction with FIG. Terminal 123 is also connected to the input side of pulse control circuit 100 via terminal 128.

The numerical output side of the switching device 114 is the control-comparison section 1
The output side of the comparator 119 is connected to the input side A of the digital multiplier 129. Fixed value memory 118
The numerical output side of is connected to the numerical input side of the multiplier 129. Numerical output side “A×B” is P
(ID) Connected to the input side of the pulse control circuit 100 via the control device 61 and the terminal device 130.
A signal depending on the polarity of the control deviation is also supplied to the pulse control circuit 100 via a terminal 131.

The operation of the control device shown in FIG. 4 will now be explained using FIGS. 5 and 6. First, the process of restarting the set value-speed previously stored in the memory device 46 will be described. Activation of the restart key 14 causes a corresponding signal U14 to appear at the terminal 101.
This signal causes the OR element 108 and the timer element 10 to
9, the counter 41 is set to a value corresponding to the actual value plus a fixed value ΔX.
Z41 (Vsoll′). Furthermore, flip-flop 104 is set and clock pulse _f4 is output to counter 41.
can reach the clock input side of the terminal 10.
It is counted up based on the 1-signal added to 7. Therefore, the ramp value increases as shown by the broken line in FIG. 5 (Z41 (Vsoll')). The frequency f ₄ depends on the set value minus the ramp value. If the difference value is greater than 10Km/h, f ₄
can be adjusted constant depending on the desired maximum acceleration by a corresponding design of the value-frequency converter 121. Therefore, the ramp value Z41(Vsoll′)
The closer to the set value Z46 (Vsoll), the smaller the frequency f ₄ becomes. This is determined by the output “B-A” of comparator 112.
This is performed under the control of the frequency converter 121. The ramp value is thereby continuously and flatly approached to the set value. The same is done for the actual value which follows the ramp value with some delay. By slowly approaching the actual value Z52 (Vist) in this way, excessive vibrations are avoided and very good riding comfort is obtained. When the ramp value reaches the set value, a 1- signal is produced at the output of comparator 112, "A=B", which resets flip-flop 104. AND gate 106 thereby prevents a subsequent counting process. Furthermore, the switching device 1
14 is activated so that instead of the ramp value of counter 41 , the setpoint value of terminal 120 can now be supplied to control-comparison unit 119 . Multiplier 1 on the control deviation value
At 29, the actual value is multiplied by a multiplication factor (coefficient) to improve the stability in small speed ranges. That is, for example, for relatively large speeds the multiplication factor is 1, while for small speeds the factor is 0.3, which reduces the amplification of the controller for relatively small speeds. Ru. This coefficient can be determined in the fixed value memory 118 by controlling the corresponding address via the actual value of the speed.
can be made smaller in practice continuously. Therefore,
Each speed - one predetermined multiplication factor (multiplying factor) for the actual value
can be made to correspond. The pulse control circuit 100 is controlled by the multiplied control deviation via the controller 61, as will be described in detail with reference to FIG.

The set value memorized at the same time is the actual value (terminal 10
7), flip-flop 19 is reset by actuation of one of keys 14-16 (signal at terminal 123), and key 15 is not actuated (and gate 110
signal at the output side), then the AND gate 12
A set signal for counter 116 and flip-flop 125 is generated at the output of 4.

The counter 116 is supplied with the instantaneous actual value. This actual value is counted down by clock signal _f5 . Flip-flop 1 when passing zero point
A reset signal for 25 is generated, resulting in a 1 signal appearing at terminal 127 during the countdown. The length of this signal is dependent on the actual value, by means of which the adjusting device 79 is controlled into a position that depends on the actual value, as will be explained in more detail with reference to FIG. The regulating device 79 is returned to the zero position (0 signal at terminal 123) after each actuation of the brake, clutch or after switching off the control device, so that by supplying the actual value via the regulating device 79 the desired speed value can be reached. is promoted. Its actual value is supplied at maximum adjustment speed, independent of control deviations. This is accomplished by the logical combination of AND gate 124 in the following cases. That is, upon activation of the acceleration key (signal at terminal 103), upon activation of the restart key (signal at terminal 101), activation of the deceleration key 15 if the stored speed value to be supplied is greater than the actual value. In case of release (terminal 1
signal trailing edge at 02).

FIG. 6 shows a case where, after actuation of the restart key 14, it is not possible to follow a ramp value whose actual value changes based on, for example, the slope of the road. If the difference between these two values were to become too large, the lamp could deviate arbitrarily far from the actual value. When the load is then removed, the vehicle is forced to accelerate excessively (full throttle). This is prevented in the following way: if the deviation >ΔY, a 0 signal is generated at the output of the comparator 122, which blocks the AND gate 106 for the clock signal f ₄ . It is to make it. The lamp will then be stopped for a short time, but will immediately continue working again. If the deviation is <ΔY again due to the increasing actual value, it continues to work again. With such a disconnection and active connection of the counting frequency to the lamp, its slope becomes small and parallel to the actual value. By adapting the ramp slope to the actual value slope, a smooth transition to the setpoint speed is achieved even in the case of multiple slopes.

The operation in the case of acceleration based on the actuation of the acceleration key 16 is performed approximately as shown in FIG. The difference is that a value obtained by adding ΔX to the actual value is once again transmitted into the counter 41 as an initial value.
As a result of the signal at the output of the OR gate 111, the numerical input A in the comparator 112 is set to the value 0, thereby producing the maximum value of the difference "B-A". This again results in the highest lamp frequency f ₄ . Upon deactivation of key 16, the instantaneously occurring actual value is supplied to setpoint memory device 46, as shown in FIG. Unlike the first embodiment, the ramp value that appears at this point
Z41 (Vsoll') remains in the counter 41, but this no longer has an influence, since at the same time the changeover device 114 to the setpoint-memory device 46
This is because switching is performed.

The circuit of FIG. 7 shows an advantageous embodiment of the pulse control circuit 100. Via terminal 150, a clock frequency f ₆ is applied to the set input of counter 151 and to the set input of flip-flop 152.
A further higher clock frequency f ₇ , for example the frequency of rotational speed generator 47 , is supplied via terminal 153 to clock input C of counter 151 . A numerical input side of the controller 61 is connected to a numerical input side of the counter 151 via the terminal device 130 . Overflow output side CO of counter 151
is connected to the reset input of a flip-flop 152, the output of which is connected to the inputs of two AND gates 154, 155, respectively. Terminal 131 is AND gate 1
54 and the second input side of AND gate 155.
Connected to the inverting input side. and gate 1
The output side of 54 is connected to the input side of an AND gate 157 via an OR gate 156, and the normal rotation operation V of the adjustment drive section 79 is controlled by the output of this AND gate. The output side of the AND gate 155 is connected to the input side of an AND gate 159 via an AND gate 158.
The reverse rotation operation R of the adjusting drive device 79 is controlled by the output of the adjusting drive device 79 via the OR gate 160. terminal 127
is connected to another input of OR gate 156 and to another inverting input of AND gate 158.
Terminal 128 is connected to a respective further inverting input of AND gates 157 , 159 and via a timing element 161 to a further input of OR gate 160 .

According to the operation of the pulse control circuit 100 shown in FIG. 7, a binary number applied to the terminal device 130 is converted into a pulse train having an impulse coefficient proportional to the binary number. What is important then is that the pulses of these output pulse trains have an integral multiple of the period or half-period of the input pulse train. This is particularly important when implementing the control device with a microcomputer, since parallel processing is then not possible. Therefore, during the measurement period (phase) after each control cycle, the engine is operated at a rotation speed generator period (half period) determined by the calculation.
controlled by In the diagram shown in FIG. 8, a varying binary number Z130 is shown. With each rising edge of signal edge f ₆ the binary digit added at that moment is transmitted into counter 151 . At the same time, flip-flop 152 is set. The transmitted value is counted down at the relatively high clock frequency _f7 , and flip-flop 152 is reset in case of an overflow pulse. Thereby, at the output of the flip-flop 152, a signal train U with an impulse coefficient proportional to the binary number Z130 is applied.
152 appears.

Corresponding to the signal applied to terminal 131 for determining the adjustment direction, its signal sequence U152 appears at one of the outputs of AND gates 154, 155. A 0-signal (non-forward operation of the adjusting drive 79 according to the actual value) appears at the terminal 127;
If a 1- signal appears at the terminal 128 (for example, failure to shut off the regulating drive by means of a brake), the outputs of the AND gates 154 and 156 can alternatively cause the pulse control circuit 100 to be activated depending on the regulating direction.
One of the outputs V to R of is controlled.
The pulse train U152 then acts on the forward or reverse rotation of the adjusting drive 79. If, as explained with reference to FIG. 4, a normal rotation signal is generated at the terminal 127 for the regulating drive 79 according to the actual value, the AND gate 158 is blocked and the signal acts directly on the output V. .

When a 1 signal is applied to terminal 128 due to a blocking process (e.g. braking), AND gate 157,1
59 is blocked and the pulse train U152 can no longer reach the adjusting drive 79. The 1- signal triggers the timing element 161, thereby
During the holding time of the timing element, a reversal signal for the adjusting drive 79 is generated at the output R. This reversal signal returns the adjustment drive 79 to the 0-position.

Of course, the adjustment drive device 79
0 output, and an amplifier stage must be inserted and connected therebetween. Such a final stage arrangement is known from German Patent Application No. 2609842. Furthermore, instead of frequency f ₇ ,
The output frequency of rotational speed generator 47 can advantageously be used.

FIG. 9 shows initialization circuitry for memory devices (eg, flip-flops and counters). The or gate 17 as in the apparatus of FIG.
The input side of the memory device is connected to a device for initializing, ie resetting, the memory device. The main switch 11 is connected to the dynamic input side of its OR gate 17. The output terminal 26 is the actual value -
It is connected to all memory devices except memory device 52, set value memory device 46 and ramp value memory device 41, which are reset to their basic positions upon the output signal of OR gate 17. The terminal 26 is connected to the trigger input side of the timer 171 via a NOR gate 170,
The output side of the timing element includes memory devices 41, 46,
52 and to the set input side of operating memory (RAM) 172. The numerical output side of this operation memory 172 is connected to the numerical input side A of the comparator 173, and the output side of this comparator "A=B" is
Connected to another input of NOR gate 170. A fixed binary number is supplied to the numerical input side B of the comparator 173 and to the numerical input side of the operating memory 172.

According to the operation of the initialization circuit shown in FIG. 9, upon closing of the main switch 11, i.e. upon activation of the device, the output of the OR gate 17 is activated after a short 1- signal due to the dynamic input of the OR gate 17. 0 again
- A signal appears. Initially, the condition “A=B” is not satisfied in the comparator 173, so
Timing element 171 is triggered and memory device 4
1, 46, 52 are reset. At the same time 2
The base number Z is delivered into operational memory 172 so that the "A=B" condition is now satisfied and NOR gate 170 is held blocked for any other type of signal at terminal 26. As a result, continued blocking of the memory devices 41, 46, 52 is no longer possible even with noise pulses on the input side. Resetting of the memory devices 41, 46, 52 is only possible again when the voltage supply is connected and the main switch 11 is closed again.

The operating functions of the devices mentioned above can advantageously be realized by a microcomputer, in particular a commercially available one-chip computer. Thereby,
It can be easily and inexpensively realized with a small space requirement. Each of the operating functions described above is entered into such a microcomputer as a program in a format familiar to those skilled in the art.

Next, in the form of a table, commercially available components that can be used, for example, in the circuit described above are presented. Those parts are indicated by model number. Manufacturers shown in parentheses are illustrative only and do not represent the only manufacturer of each component.

1-chip microcomputer 8048 or 8021
(Intel) Fixed value memory (ROM) CDP1833CD (RCA) Digital counter 4029 (RCA) Digital comparator MC14585 (Motorola) Operating memory (RAM) CDP1824 (RCA) Subtractor (adder) CD40181B (RCA) Multiplier CD4527B (RCA) Multiplexer 4052 (RCA) Numerical value-frequency converter SN7497N (TI)