JPS6418327U - - Google Patents
Info
- Publication number
- JPS6418327U JPS6418327U JP11307087U JP11307087U JPS6418327U JP S6418327 U JPS6418327 U JP S6418327U JP 11307087 U JP11307087 U JP 11307087U JP 11307087 U JP11307087 U JP 11307087U JP S6418327 U JPS6418327 U JP S6418327U
- Authority
- JP
- Japan
- Prior art keywords
- battery
- memory pack
- comparator
- power source
- reference power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の一実施例を示す概略構成図、
第２図は従来のバツテリチエツクを示す概略回路
図である。
１：メモリパツク、２：メモリ、３：バツテリ
、４：雌形コネクタ、５：チエツク装置、６：基
準電源、７：コンパレータ、８：発光素子、９：
雄形コネクタ。
FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram showing a conventional battery check. 1: Memory pack, 2: Memory, 3: Battery, 4: Female connector, 5: Check device, 6: Reference power supply, 7: Comparator, 8: Light emitting element, 9:
Male connector.
Claims (1)
力端子に前記基準電源が接続された低消費電流形
コンパレータと、このコンパレータの出力信号に
よつて駆動されるアラーム発信手段と、前記コン
パレータの他方の入力端子に接続されたコネクタ
とを備え、このコネクタを、チエツクすべきメモ
リパツク内バツテリの端子から導出されたメモリ
パツクコネクタに、前記コンパレータに前記基準
電源とバツテリとが同極性にて接続されるように
結合することを特徴とするメモリパツク内バツテ
リのチエツク装置。 a reference power source, a low current consumption comparator having two input terminals, one input terminal of which is connected to the reference power source; an alarm generating means driven by an output signal of the comparator; and a connector connected to the other input terminal, and this connector is connected to the memory pack connector derived from the terminal of the battery in the memory pack to be checked, and the reference power source and the battery are connected to the comparator with the same polarity. A battery checking device in a memory pack, characterized in that the battery is connected in such a manner that the memory pack is connected in such a manner as to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11307087U JPS6418327U (en) | 1987-07-23 | 1987-07-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11307087U JPS6418327U (en) | 1987-07-23 | 1987-07-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6418327U true JPS6418327U (en) | 1989-01-30 |
Family
ID=31352583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11307087U Pending JPS6418327U (en) | 1987-07-23 | 1987-07-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6418327U (en) |
-
1987
- 1987-07-23 JP JP11307087U patent/JPS6418327U/ja active Pending
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