JPS6418863A - Multiplexing system for input/output interface - Google Patents

Multiplexing system for input/output interface

Info

Publication number
JPS6418863A
JPS6418863A JP17557787A JP17557787A JPS6418863A JP S6418863 A JPS6418863 A JP S6418863A JP 17557787 A JP17557787 A JP 17557787A JP 17557787 A JP17557787 A JP 17557787A JP S6418863 A JPS6418863 A JP S6418863A
Authority
JP
Japan
Prior art keywords
interface
access
input
address
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17557787A
Other languages
Japanese (ja)
Other versions
JP2543710B2 (en
Inventor
Sukenao Tanigawa
Toshiharu Oshima
Yasuhiro Futaoka
Kenichi Abo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62175577A priority Critical patent/JP2543710B2/en
Publication of JPS6418863A publication Critical patent/JPS6418863A/en
Application granted granted Critical
Publication of JP2543710B2 publication Critical patent/JP2543710B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To realize the use of the same processor even in a system requiring no multiplication by multiplexing an input/output interface with no multiplexing applied to an access function part of a processor so that the direct memory accesses can be transferred in parallel with each other. CONSTITUTION:A complementary interface 12 is connected as an option to a basic interface 11 via an interface converter circuit 5. The access transfer controllers 3 and 4 are connected to each interface against a memory 2. Then an access is first given to a basic interface 11 since an address is given from a processor 1. The circuit 5 monitors said access and connects the interface 12 to the interface 11 if the relevant address belongs to the interface 12 and sends the address to the interface 12 for execution of the DMA transfer.
JP62175577A 1987-07-14 1987-07-14 Input / output interface multiplex system Expired - Lifetime JP2543710B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62175577A JP2543710B2 (en) 1987-07-14 1987-07-14 Input / output interface multiplex system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62175577A JP2543710B2 (en) 1987-07-14 1987-07-14 Input / output interface multiplex system

Publications (2)

Publication Number Publication Date
JPS6418863A true JPS6418863A (en) 1989-01-23
JP2543710B2 JP2543710B2 (en) 1996-10-16

Family

ID=15998517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62175577A Expired - Lifetime JP2543710B2 (en) 1987-07-14 1987-07-14 Input / output interface multiplex system

Country Status (1)

Country Link
JP (1) JP2543710B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5932025A (en) * 1982-08-16 1984-02-21 Fujitsu Ltd Bidirectional bus extending system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5932025A (en) * 1982-08-16 1984-02-21 Fujitsu Ltd Bidirectional bus extending system

Also Published As

Publication number Publication date
JP2543710B2 (en) 1996-10-16

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