JPS6419778A - Electrostatic induction type field-effect transistor - Google Patents

Abstract

PURPOSE:To enable an OFF operation at a low control voltage for an improved yield by a method wherein a plurality of gate layers, each provided with a plurality of gate electrodes positioned with a prescribed distance between, are buried in a channel-forming region. CONSTITUTION:Cr is attached by vapor depositing or the like to an insulating glass substrate 1 for the formation of a drain electrode film 10, and a strongly N-type drain layer 11 is grown by the plasma CVD method. The plasma CVD method is used again in a process of forming an amorphous silicon layer 21, which is followed by a process wherein a very thin Pt film is attached to the amorphous silicon layer 21 by spattering. The Pt-coated amorphous silicon layer 21 is subjected to a photoprocess whereby it is converted into a gate layer 31 divided into a plurality of gate electrodes 31a. Similarly, an amorphous silicon layer 22 is grown and converted into a gate layer 32 whose plurality of gate electrodes 32a will be caused to locate themselves between the gate electrodes 31a belonging to the gate layer 31. A third amorphous silicon layer 23 is then formed thereon. A process follows wherein an amorphous silicon layer is formed for a strongly N-type source layer 40 and aluminum is attached thereto for a source electrode film 41.