JPS6420719U - - Google Patents
Info
- Publication number
- JPS6420719U JPS6420719U JP11461187U JP11461187U JPS6420719U JP S6420719 U JPS6420719 U JP S6420719U JP 11461187 U JP11461187 U JP 11461187U JP 11461187 U JP11461187 U JP 11461187U JP S6420719 U JPS6420719 U JP S6420719U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- capacitor
- capacitors
- series
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Protection Of Static Devices (AREA)
Description
第１図は本考案の原理説明図、第２図は本考案
の一実施例である二重化コンデンサ、第３図は本
考案の他の実施例である三重化コンデンサである
。
図中、Ａ，Ｂ…多重化コンデンサの端子、Ｃ１
〜ＣＮ…コンデンサ、Ｆ１〜Ｆ（Ｎ−１）…ヒユ
ーズ、Ｔ１〜Ｔ（Ｎ−１）…各コンデンサの一端
子。
FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a duplex capacitor which is one embodiment of the present invention, and FIG. 3 is a triple capacitor which is another embodiment of the present invention. In the figure, A, B...terminals of multiplexing capacitor, C1
~CN...Capacitor, F1~F(N-1)...Fuse, T1~T(N-1)...One terminal of each capacitor.
Claims (1)
Ｎを直列に接続し、該コンデンサ直列回路の一端
子Ｂと、前記Ｎ個のコンデンサＣ１〜ＣＮのうち
前記一端子Ｂから遠い側のＮ−１個のコンデンサ
Ｃ１〜Ｃ（Ｎ−１）の前記一端子Ｂ側の各端子Ｔ
１〜Ｔ（Ｎ−１）との間にヒユーズＦ１〜Ｆ（Ｎ
−１）を並列接続したことを特徴とする多重化コ
ンデンサ。 ２ 前記Ｎが２であり、第１のコンデンサの一端
子に、ヒユーズと第２のコンデンサとを並列接続
した回路を直列接続して成る実用新案登録請求の
範囲第１項記載の多重化コンデンサ。[Claims for Utility Model Registration] 1 N capacitors C1 to C having the same characteristics
N are connected in series, and one terminal B of the capacitor series circuit and N-1 capacitors C1 to C (N-1) on the side far from the one terminal B among the N capacitors C1 to CN (N-1). Each terminal T on the one terminal B side
1 to T(N-1), fuses F1 to F(N
-1) are connected in parallel. 2. The multiplexing capacitor according to claim 1, wherein N is 2, and a circuit in which a fuse and a second capacitor are connected in parallel is connected in series to one terminal of the first capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11461187U JPS6420719U (en) | 1987-07-28 | 1987-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11461187U JPS6420719U (en) | 1987-07-28 | 1987-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6420719U true JPS6420719U (en) | 1989-02-01 |
Family
ID=31355513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11461187U Pending JPS6420719U (en) | 1987-07-28 | 1987-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6420719U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7530350B2 (en) | 2006-06-23 | 2009-05-12 | Denso Corporation | Output circuit for an on-vehicle electronic device |
-
1987
- 1987-07-28 JP JP11461187U patent/JPS6420719U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7530350B2 (en) | 2006-06-23 | 2009-05-12 | Denso Corporation | Output circuit for an on-vehicle electronic device |
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