JPS6421790A - Dram controller with page mode function - Google Patents

Dram controller with page mode function

Info

Publication number
JPS6421790A
JPS6421790A JP62177177A JP17717787A JPS6421790A JP S6421790 A JPS6421790 A JP S6421790A JP 62177177 A JP62177177 A JP 62177177A JP 17717787 A JP17717787 A JP 17717787A JP S6421790 A JPS6421790 A JP S6421790A
Authority
JP
Japan
Prior art keywords
page mode
mode function
comparison
address information
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62177177A
Other languages
Japanese (ja)
Inventor
Yoshiki Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP62177177A priority Critical patent/JPS6421790A/en
Publication of JPS6421790A publication Critical patent/JPS6421790A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dram (AREA)

Abstract

PURPOSE:To effectively use a page mode function, and to shorten access time by selecting a first generator when all bits coincide based on the result of comparison. CONSTITUTION:The respective bits, to which row address information RA(n) in a present cycle, outputted from a controlling means 1, and the row address information RA(n-1) of a previous cycle, latched by an address latch circuit 2, correspond, are compared in an address comparison circuit 3 respectively, and when all the bits coincide based on the result of this comparison, the first generator 4 is selected. In addition, the controlling means 1 outputs address information and an address control signal, the inverse of AS in response to a cycle finish signal from either the first and second generators 4, 5. Thus, because the page mode function is effectively used, the access time can be shortened.
JP62177177A 1987-07-17 1987-07-17 Dram controller with page mode function Pending JPS6421790A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62177177A JPS6421790A (en) 1987-07-17 1987-07-17 Dram controller with page mode function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62177177A JPS6421790A (en) 1987-07-17 1987-07-17 Dram controller with page mode function

Publications (1)

Publication Number Publication Date
JPS6421790A true JPS6421790A (en) 1989-01-25

Family

ID=16026527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62177177A Pending JPS6421790A (en) 1987-07-17 1987-07-17 Dram controller with page mode function

Country Status (1)

Country Link
JP (1) JPS6421790A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352188A (en) * 1989-07-19 1991-03-06 Nec Corp Storage device
WO1991006956A1 (en) * 1989-11-07 1991-05-16 Fujitsu Limited Semiconductor memory device
US5715421A (en) * 1992-10-16 1998-02-03 Seiko Epson Corporation Apparatus and method of addressing paged mode memory including adjacent page precharging

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134991A (en) * 1984-12-06 1986-06-23 Toshiba Corp Access method of dynamic memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134991A (en) * 1984-12-06 1986-06-23 Toshiba Corp Access method of dynamic memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352188A (en) * 1989-07-19 1991-03-06 Nec Corp Storage device
WO1991006956A1 (en) * 1989-11-07 1991-05-16 Fujitsu Limited Semiconductor memory device
US5335206A (en) * 1989-11-07 1994-08-02 Fujitsu Limited Semiconductor storage device
EP0452510B1 (en) * 1989-11-07 1996-01-17 Fujitsu Limited Semiconductor memory device
US5715421A (en) * 1992-10-16 1998-02-03 Seiko Epson Corporation Apparatus and method of addressing paged mode memory including adjacent page precharging

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