JPS6422142A - Packet transfer processing system - Google Patents

Packet transfer processing system

Info

Publication number
JPS6422142A
JPS6422142A JP17835687A JP17835687A JPS6422142A JP S6422142 A JPS6422142 A JP S6422142A JP 17835687 A JP17835687 A JP 17835687A JP 17835687 A JP17835687 A JP 17835687A JP S6422142 A JPS6422142 A JP S6422142A
Authority
JP
Japan
Prior art keywords
page
bursts
normally received
burst
packet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17835687A
Other languages
Japanese (ja)
Inventor
Yoshitaka Hirano
Hideki Kataoka
Tatsuro Takahashi
So Sakakibara
Shiro Kikuchi
Motoyuki Ishikawa
Akira Inaba
Arata Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
NTT Inc
Original Assignee
Toshiba Corp
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Nippon Telegraph and Telephone Corp filed Critical Toshiba Corp
Priority to JP17835687A priority Critical patent/JPS6422142A/en
Publication of JPS6422142A publication Critical patent/JPS6422142A/en
Pending legal-status Critical Current

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To improve a line using efficiency and a packet processing efficiency by transferring a normally received packet only. CONSTITUTION:On the way of the receiving of a first packet from four bursts (a)-(d), the burst sequence abnormality occurs, and bursts (a) and (b) are normally received and the burst (c) is not normally received, the bursts (a) and (b) are respectively stored to first page and third page of a buffer memory 13 and the linked by a linkage memory 14. In such a condition, when the abnormality occurs, the page information to an output queue 110 is not transferred, and concerning the page in which the input is already completed, all axcluding all parts or the leading burst are made into the lost page, and registered as an idle page automatically by an overlapped loast page detecting correcting circuit. Thus, the unnecessary data in the buffer are abolished.
JP17835687A 1987-07-17 1987-07-17 Packet transfer processing system Pending JPS6422142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17835687A JPS6422142A (en) 1987-07-17 1987-07-17 Packet transfer processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17835687A JPS6422142A (en) 1987-07-17 1987-07-17 Packet transfer processing system

Publications (1)

Publication Number Publication Date
JPS6422142A true JPS6422142A (en) 1989-01-25

Family

ID=16047057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17835687A Pending JPS6422142A (en) 1987-07-17 1987-07-17 Packet transfer processing system

Country Status (1)

Country Link
JP (1) JPS6422142A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543707A (en) * 1992-09-30 1996-08-06 Seiko Epson Corporation Digital tester

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543707A (en) * 1992-09-30 1996-08-06 Seiko Epson Corporation Digital tester
US5581175A (en) * 1992-09-30 1996-12-03 Seiko Epson Corporation Digital tester with probe storage features

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