JPS6423344A - Test system for data processor - Google Patents

Test system for data processor

Info

Publication number
JPS6423344A
JPS6423344A JP62178896A JP17889687A JPS6423344A JP S6423344 A JPS6423344 A JP S6423344A JP 62178896 A JP62178896 A JP 62178896A JP 17889687 A JP17889687 A JP 17889687A JP S6423344 A JPS6423344 A JP S6423344A
Authority
JP
Japan
Prior art keywords
test
data
expected value
carried out
instruction train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62178896A
Other languages
Japanese (ja)
Inventor
Hiroshi Kadota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62178896A priority Critical patent/JPS6423344A/en
Publication of JPS6423344A publication Critical patent/JPS6423344A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To localize and analyze the range of test instructions and to shorten the checking time for a test system for data processor, by executing the prescribed one of test instruction trains and performing the comparison of the check results at the check point passing time point. CONSTITUTION:An instruction train 16a set at an executing area 16 is traced as the expected value as long as the generation of a trap does not show the end of a test instruction train after the trap generation is detected through a check point in a simulation mode. Then the tracing result is saved as the expected value in case the trap generation shows the end of the test instruction train after a trace instruction train is carried out. It is checked whether the test instructions are carried out up to the last one or not after a test instruction train containing the same test data is carried out on a device to be tested and the trap generation is detected. If the test instructions are not carried out up to the last one, the comparison check 11 is performed based on the contents of the expected value and the order of the trace data. When the abnormality is detected, a test instruction train is delivered together with the test data, the trace data, the expected value of data and the execution result. Then the factors of the abnormality are studied.
JP62178896A 1987-07-20 1987-07-20 Test system for data processor Pending JPS6423344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62178896A JPS6423344A (en) 1987-07-20 1987-07-20 Test system for data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62178896A JPS6423344A (en) 1987-07-20 1987-07-20 Test system for data processor

Publications (1)

Publication Number Publication Date
JPS6423344A true JPS6423344A (en) 1989-01-26

Family

ID=16056586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62178896A Pending JPS6423344A (en) 1987-07-20 1987-07-20 Test system for data processor

Country Status (1)

Country Link
JP (1) JPS6423344A (en)

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