JPS6423619A - Counter circuit - Google Patents

Counter circuit

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Publication number
JPS6423619A
JPS6423619A JP17953587A JP17953587A JPS6423619A JP S6423619 A JPS6423619 A JP S6423619A JP 17953587 A JP17953587 A JP 17953587A JP 17953587 A JP17953587 A JP 17953587A JP S6423619 A JPS6423619 A JP S6423619A
Authority
JP
Japan
Prior art keywords
circuit
reset pulse
gate
input pulses
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17953587A
Other languages
Japanese (ja)
Inventor
Katsutoshi Miyaji
Shiyunichi Magome
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17953587A priority Critical patent/JPS6423619A/en
Publication of JPS6423619A publication Critical patent/JPS6423619A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a further miniaturized counter circuit, by constituting the circuit by means of the combination of an n-stage dividing circuit and gate circuits which control the initializing state of the dividing circuit. CONSTITUTION:The titled circuit is provided with an n-stage dividing circuit 10 which is equipped with stages of a number equivalent to (n) and divides input pulses (1) in accordance with the number of the (n) and, at the same time, which is reset by a reset pulse (2), a 1st gate circuit 20 which outputs a prescribed value when the output (4) of a 2nd gate circuit 30 and the output of each stage of the circuit 10 become prescribed values and another value when the reset pulse (2) is inputted, and the 2nd gate circuit 30. By inputting the reset pulse (2), the n-stage dividing circuit 10 is set to the initialized state and, for example, the fall of 2n pieces of input pulses (1) is divided. Then the input pulses (1) are controlled by using the output of the 1st gate circuit 20 at the moment when the 2n-th input pulse (1) is inputted so that the further input of the input pulses (1) can be inhibited until the next reset pulse (2) is inputted. Therefore, a further miniaturized counter circuit can be realized.
JP17953587A 1987-07-17 1987-07-17 Counter circuit Pending JPS6423619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17953587A JPS6423619A (en) 1987-07-17 1987-07-17 Counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17953587A JPS6423619A (en) 1987-07-17 1987-07-17 Counter circuit

Publications (1)

Publication Number Publication Date
JPS6423619A true JPS6423619A (en) 1989-01-26

Family

ID=16067453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17953587A Pending JPS6423619A (en) 1987-07-17 1987-07-17 Counter circuit

Country Status (1)

Country Link
JP (1) JPS6423619A (en)

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