JPS642421A - Receiver - Google Patents

Receiver

Info

Publication number
JPS642421A
JPS642421A JP62158190A JP15819087A JPS642421A JP S642421 A JPS642421 A JP S642421A JP 62158190 A JP62158190 A JP 62158190A JP 15819087 A JP15819087 A JP 15819087A JP S642421 A JPS642421 A JP S642421A
Authority
JP
Japan
Prior art keywords
signal
threshold level
level
locking
pll demodulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62158190A
Other languages
Japanese (ja)
Other versions
JPH012421A (en
JPH0734548B2 (en
Inventor
Seiji Sakashita
Hiroaki Ozeki
Ippei Jinno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15819087A priority Critical patent/JPH0734548B2/en
Publication of JPH012421A publication Critical patent/JPH012421A/en
Publication of JPS642421A publication Critical patent/JPS642421A/en
Publication of JPH0734548B2 publication Critical patent/JPH0734548B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE: To improve a threshold level by combining a locking range expansion type PLL demodulator which expands a locking range with a tracking BPF.
CONSTITUTION: The output signal of one phase comparator of the locking range expansion type PLL demodulator is used as a signal for gain control and a signal for varying the band width of a loop filter. Consequently, while a phase locked state is detected, attenuation by the tracking BPF 2 is corrected and the level of an input signal to the phase comparator is made constant to stabilize phase locking operation. Further, the band width is optimized by varying the electrode and zero point of the LPF to improve the threshold level. Thus, the input signal level of the PLL demodulator is made constant and the electrode and zero point frequency of the LPF is varied to suppress variation in loop gain, so the locking operation is stabilized and the threshold level is improved.
COPYRIGHT: (C)1989,JPO&Japio
JP15819087A 1987-06-25 1987-06-25 Receiver Expired - Lifetime JPH0734548B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15819087A JPH0734548B2 (en) 1987-06-25 1987-06-25 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15819087A JPH0734548B2 (en) 1987-06-25 1987-06-25 Receiver

Publications (3)

Publication Number Publication Date
JPH012421A JPH012421A (en) 1989-01-06
JPS642421A true JPS642421A (en) 1989-01-06
JPH0734548B2 JPH0734548B2 (en) 1995-04-12

Family

ID=15666232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15819087A Expired - Lifetime JPH0734548B2 (en) 1987-06-25 1987-06-25 Receiver

Country Status (1)

Country Link
JP (1) JPH0734548B2 (en)

Also Published As

Publication number Publication date
JPH0734548B2 (en) 1995-04-12

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