JPS642446U - - Google Patents
Info
- Publication number
- JPS642446U JPS642446U JP1987096705U JP9670587U JPS642446U JP S642446 U JPS642446 U JP S642446U JP 1987096705 U JP1987096705 U JP 1987096705U JP 9670587 U JP9670587 U JP 9670587U JP S642446 U JPS642446 U JP S642446U
- Authority
- JP
- Japan
- Prior art keywords
- dielectric substrate
- integrated circuit
- hole
- side wall
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案に係る実装構造の一実施例の構
成図、イ図は斜視図、ロ図はイ図のＡ−Ａ′断面
図、第２図は従来の実装構造の構成図で、イ図は
斜視図、ロ図はイ図のＡ−Ａ′断面図、第３図及
び第４図は従来例に対する本考案の特徴を説明す
る為の図である。
１……集積回路、２……誘電体基板、２ａ……
穴、３……ヒートシンク、４……外部回路、５，
７……ボンデイングワイヤ、８……側壁導体面。
Fig. 1 is a block diagram of an embodiment of the mounting structure according to the present invention, Fig. A is a perspective view, Fig. B is a sectional view taken along line A-A' in Fig. A, and Fig. 2 is a block diagram of a conventional mounting structure. Figure A is a perspective view, Figure B is a sectional view taken along line A-A' in Figure A, and Figures 3 and 4 are diagrams for explaining the features of the present invention compared to the conventional example. 1... Integrated circuit, 2... Dielectric substrate, 2a...
Hole, 3...Heat sink, 4...External circuit, 5,
7...Bonding wire, 8...Side wall conductor surface.
Claims (1)
シンク上に配置された誘電体基板、及びこの誘電
体基板の面とその面が面一化されるように前記穴
内に落し込まれ前記ヒートシンク上に固定配置さ
れた集積回路を具備し、この集積回路と誘電体基
板に形成した外部回路及び集積回路と前記側壁導
体面とを夫々ボンデイングワイヤで接続したこと
を特徴とする集積回路の実装構造。 A dielectric substrate in which a hole is formed and the side wall of the hole is used as a conductive surface and is placed on the heat sink, and a dielectric substrate is dropped into the hole and placed on the heat sink so that the surface of the dielectric substrate is flush with the surface of the dielectric substrate. A mounting structure for an integrated circuit, comprising a fixedly arranged integrated circuit, and the integrated circuit, an external circuit formed on a dielectric substrate, and the integrated circuit and the side wall conductor surface are connected by bonding wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987096705U JPS642446U (en) | 1987-06-24 | 1987-06-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987096705U JPS642446U (en) | 1987-06-24 | 1987-06-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS642446U true JPS642446U (en) | 1989-01-09 |
Family
ID=31321777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987096705U Pending JPS642446U (en) | 1987-06-24 | 1987-06-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS642446U (en) |
-
1987
- 1987-06-24 JP JP1987096705U patent/JPS642446U/ja active Pending