JPS6425251A - System for debugging program - Google Patents

System for debugging program

Info

Publication number
JPS6425251A
JPS6425251A JP62182779A JP18277987A JPS6425251A JP S6425251 A JPS6425251 A JP S6425251A JP 62182779 A JP62182779 A JP 62182779A JP 18277987 A JP18277987 A JP 18277987A JP S6425251 A JPS6425251 A JP S6425251A
Authority
JP
Japan
Prior art keywords
program
address
comparator
address information
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62182779A
Other languages
Japanese (ja)
Inventor
Jitsuo Sentoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62182779A priority Critical patent/JPS6425251A/en
Publication of JPS6425251A publication Critical patent/JPS6425251A/en
Pending legal-status Critical Current

Links

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To improve a debugging efficiency by providing a comparator to compare address information outputted when a controller reads a program, with the address information designated by an input/output device and a counting circuit to count a coincidence signal outputted from comparator. CONSTITUTION:An address storage circuit 3 stores the address information of the program designated by a command inputted with a typewriter 6 of the input/output device. Every time a controller 1 reads the program of a program storing memory 2, a comparator 4 compares a read address signal with the address information stored by the address storage circuit 3, and only when the signal and the information coincide, the circuit 4 outputs a coincidence signal. A counting circuit 5 steps a counting value at every receiving the coincidence signal and outputs the frequency of the execution of the program of a designated address through the controller 1 to the typewriter 6.
JP62182779A 1987-07-21 1987-07-21 System for debugging program Pending JPS6425251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62182779A JPS6425251A (en) 1987-07-21 1987-07-21 System for debugging program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62182779A JPS6425251A (en) 1987-07-21 1987-07-21 System for debugging program

Publications (1)

Publication Number Publication Date
JPS6425251A true JPS6425251A (en) 1989-01-27

Family

ID=16124271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62182779A Pending JPS6425251A (en) 1987-07-21 1987-07-21 System for debugging program

Country Status (1)

Country Link
JP (1) JPS6425251A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378738A (en) * 1976-12-23 1978-07-12 Toshiba Corp Memory control system
JPS5658199A (en) * 1979-10-18 1981-05-21 Nec Corp Address comparisons stop circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378738A (en) * 1976-12-23 1978-07-12 Toshiba Corp Memory control system
JPS5658199A (en) * 1979-10-18 1981-05-21 Nec Corp Address comparisons stop circuit

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