JPS6428735A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS6428735A
JPS6428735A JP18332587A JP18332587A JPS6428735A JP S6428735 A JPS6428735 A JP S6428735A JP 18332587 A JP18332587 A JP 18332587A JP 18332587 A JP18332587 A JP 18332587A JP S6428735 A JPS6428735 A JP S6428735A
Authority
JP
Japan
Prior art keywords
interruption
bus
cmdl3
information
pmdl1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18332587A
Other languages
Japanese (ja)
Other versions
JPH087694B2 (en
Inventor
Makoto Muramatsu
Toshiaki Koyama
Shigeki Morimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18332587A priority Critical patent/JPH087694B2/en
Publication of JPS6428735A publication Critical patent/JPS6428735A/en
Publication of JPH087694B2 publication Critical patent/JPH087694B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To efficiently transfer an interruption request and interruption information without giving effect on substantial data transfer by providing an interruption exclusive bus in common to each module for input/output device control and a processor. CONSTITUTION:Processor modules PMDL1a-1n and input/output device control modules EMDL2a-2m are connected by a common bus 4 and the EMDL2 and the interruption control module CMDL3 are connected by an interruption bus 5 and the PMDL1 and the CMDL3 are connected by an interruption bus 6. Then the CMDL3 extracts the interruption request caused in each EMDL2 and its interrupt information via the bus 5 by the polling system and registers it in a storage section, and the registered interruption request and information are transferred to the corresponding PMDL1 via the bus 6 by the time division system.
JP18332587A 1987-07-24 1987-07-24 Interrupt control method Expired - Lifetime JPH087694B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18332587A JPH087694B2 (en) 1987-07-24 1987-07-24 Interrupt control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18332587A JPH087694B2 (en) 1987-07-24 1987-07-24 Interrupt control method

Publications (2)

Publication Number Publication Date
JPS6428735A true JPS6428735A (en) 1989-01-31
JPH087694B2 JPH087694B2 (en) 1996-01-29

Family

ID=16133733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18332587A Expired - Lifetime JPH087694B2 (en) 1987-07-24 1987-07-24 Interrupt control method

Country Status (1)

Country Link
JP (1) JPH087694B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03135650A (en) * 1989-10-20 1991-06-10 Fuji Photo Film Co Ltd File information transfer method
JPH04174052A (en) * 1990-11-02 1992-06-22 Nec Ic Microcomput Syst Ltd Communication control system
JP2008192128A (en) * 2007-01-11 2008-08-21 Sony Corp Information processing apparatus, information processing method, and computer program
US8645668B2 (en) 2007-01-11 2014-02-04 Sony Corporation Information processing apparatus, information processing method and computer program

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03135650A (en) * 1989-10-20 1991-06-10 Fuji Photo Film Co Ltd File information transfer method
JPH04174052A (en) * 1990-11-02 1992-06-22 Nec Ic Microcomput Syst Ltd Communication control system
JP2008192128A (en) * 2007-01-11 2008-08-21 Sony Corp Information processing apparatus, information processing method, and computer program
US8645668B2 (en) 2007-01-11 2014-02-04 Sony Corporation Information processing apparatus, information processing method and computer program

Also Published As

Publication number Publication date
JPH087694B2 (en) 1996-01-29

Similar Documents

Publication Publication Date Title
HK62581A (en) Input/output system for a multiprocessor system
AU585076B2 (en) Interrupt handling in a multiprocessor computing system
EP0231595A3 (en) Input/output controller for a data processing system
JPS6428735A (en) Interruption control system
MY116719A (en) Using intelligent bridges with pico-code to improve interrupt response
JPS5750037A (en) Data transfer system
JPS5680722A (en) Interprocessor control system
JPS56110125A (en) Data processing device
JPS5520532A (en) Control system for plural electronic cash registers
KR950004022A (en) Distributed Processing Integrated Management System
JPS5697121A (en) Bus control system
JPS57164318A (en) Information processing system
JPS5493340A (en) Duplex processing system
JPS56111931A (en) Data transfer device
JPS56143072A (en) Hung up release and processing system in multiprocessor processing system
JPS53103332A (en) Input/output control system for information processor
JPS6448160A (en) Serial interface control system
JPS5363825A (en) Input/output control system in information processing system
JPS55153021A (en) Data transfer system of multiprocessor system
JPS57136239A (en) Device address switching system
JPS51144137A (en) Input/output data control unit
JPS6459446A (en) Information processing system
JPS55153022A (en) Transmission system for input-output signal
JPS5759220A (en) Data transfer system
JPS56101228A (en) Computer system

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080129

Year of fee payment: 12

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080129

Year of fee payment: 12