JPS6429024A - Digital peak detector - Google Patents

Digital peak detector

Info

Publication number
JPS6429024A
JPS6429024A JP18480487A JP18480487A JPS6429024A JP S6429024 A JPS6429024 A JP S6429024A JP 18480487 A JP18480487 A JP 18480487A JP 18480487 A JP18480487 A JP 18480487A JP S6429024 A JPS6429024 A JP S6429024A
Authority
JP
Japan
Prior art keywords
value
held
signal
register
peak value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18480487A
Other languages
Japanese (ja)
Inventor
Shigeru Usuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18480487A priority Critical patent/JPS6429024A/en
Publication of JPS6429024A publication Critical patent/JPS6429024A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To precisely deal with a low frequency by sampling and holding an input analog signal, and digitizing a sample value, and comparing it with a previous peak value, and outputting it. CONSTITUTION:As for the input analog signal, the voltage value at that point of time is held by a sample hold circuit 2, and is converted into a digital value by an A/D converter 3, and the voltage value is held by a hold register 4. Then, the previous peak value, held in an output register 5, and the voltage value of the hold register 4 are compared by a comparator 6, and if the former is larger, the signal of '1' is outputted, and if not, the signal of '0' is outputted. Accordingly, when the output of the comparator 6 is '1', the voltage, held in the hold register 4, is set as the new peak value, in the output register 5. Thus, the peak value of the input analog signal can be outputted as a digital signal.
JP18480487A 1987-07-23 1987-07-23 Digital peak detector Pending JPS6429024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18480487A JPS6429024A (en) 1987-07-23 1987-07-23 Digital peak detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18480487A JPS6429024A (en) 1987-07-23 1987-07-23 Digital peak detector

Publications (1)

Publication Number Publication Date
JPS6429024A true JPS6429024A (en) 1989-01-31

Family

ID=16159582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18480487A Pending JPS6429024A (en) 1987-07-23 1987-07-23 Digital peak detector

Country Status (1)

Country Link
JP (1) JPS6429024A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6934646B2 (en) * 2002-10-21 2005-08-23 Agilent Technologies, Inc. Waveform complexity detector
US7230782B2 (en) 2003-08-28 2007-06-12 Quantum Corporation Correlation receiver for demodulating servo track information

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6934646B2 (en) * 2002-10-21 2005-08-23 Agilent Technologies, Inc. Waveform complexity detector
US7230782B2 (en) 2003-08-28 2007-06-12 Quantum Corporation Correlation receiver for demodulating servo track information

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