JPS6430332A - Decoder circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit as a whole by selecting one method of remainder data composing system data to execute an arithmetic processing by means of a remainder arithmetic method to a value indicated by the power method of 2, simultaneously, separating adding data corresponding to the value and executing a data processing. CONSTITUTION:One m3 among methods m0-m3 of respective remainder data DM0, DM1, DM2 and DM3 composing system (RNS) data DR0 to utilize the remainder arithmetic method and to execute the arithmetic processing is selected to the value indicated by the power method of 2. After the remainder data DM0-DM3 are multiplying-processed based on the methods m0-m3 of the remainder data through multiplying means 11-14, adding data DA are obtained through adding means 20-22. The adding data DA are separated into data DH and DL of a high-order bit and a lower-order bit base on the value indicated by the power method of 2 and by dividing-processing the data DH based on the methods m0-m2 of the remainder data DM0-DM2, the remainder data are obtained and sent along with the data DL of the low-order bit. Thus, the dividing processing of the adding data DA can be simplified.