JPS6431260A - Logical simulation method - Google Patents

Logical simulation method

Info

Publication number
JPS6431260A
JPS6431260A JP18911387A JP18911387A JPS6431260A JP S6431260 A JPS6431260 A JP S6431260A JP 18911387 A JP18911387 A JP 18911387A JP 18911387 A JP18911387 A JP 18911387A JP S6431260 A JPS6431260 A JP S6431260A
Authority
JP
Japan
Prior art keywords
file
mos type
transfer switch
processing
connecting information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18911387A
Other languages
Japanese (ja)
Inventor
Kazunaga Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18911387A priority Critical patent/JPS6431260A/en
Publication of JPS6431260A publication Critical patent/JPS6431260A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

PURPOSE:To simplify a gate and to reduce the number of elements by transforming a transfer switch to a general primitive such as an AND or an OR. CONSTITUTION:A file 101 including logical connecting information is compiled 201, thereafter, the N-MOS type or the P-MOS type wired connecting part circuit of the transfer switch is extracted by a part circuit extracting processing 202 to form file 102 and store the connecting information except it in a file 103. The N-MOS type or the P-MOS type wired connecting information of the transfer switch in the file 102 is transformed to an AND-OR logic according to the general primitive transforming processing A1. Thereby, a logical operation is correctly executed, the number of the elements is reduced and the simplifying processing of the circuit can be applied.
JP18911387A 1987-07-28 1987-07-28 Logical simulation method Pending JPS6431260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18911387A JPS6431260A (en) 1987-07-28 1987-07-28 Logical simulation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18911387A JPS6431260A (en) 1987-07-28 1987-07-28 Logical simulation method

Publications (1)

Publication Number Publication Date
JPS6431260A true JPS6431260A (en) 1989-02-01

Family

ID=16235597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18911387A Pending JPS6431260A (en) 1987-07-28 1987-07-28 Logical simulation method

Country Status (1)

Country Link
JP (1) JPS6431260A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5964665A (en) * 1996-07-03 1999-10-12 Sega Enterprises, Ltd. Vehicle playing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5964665A (en) * 1996-07-03 1999-10-12 Sega Enterprises, Ltd. Vehicle playing apparatus

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