JPS6431446U - - Google Patents
Info
- Publication number
- JPS6431446U JPS6431446U JP12540287U JP12540287U JPS6431446U JP S6431446 U JPS6431446 U JP S6431446U JP 12540287 U JP12540287 U JP 12540287U JP 12540287 U JP12540287 U JP 12540287U JP S6431446 U JPS6431446 U JP S6431446U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply voltage
- register
- occurrence
- offset data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Microcomputers (AREA)
Description
第１図は本考案の第１の実施例を示すブロツク
図、第２図は本考案の第２の実施例を示すブロツ
ク図である。
１……電源電圧の立ち上がり検出部、２……ポ
ートの入出力制御部、３……ベクタ・アドレスの
オフセツト・データ格納レジスタ、４……マイク
ロシーケンサ、５……マイクロＲＯＭ、６……プ
ログラム・カウンタ、７……演算器、８……テン
ポラリ・ラツチ。
FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 2 is a block diagram showing a second embodiment of the present invention. 1...Power supply voltage rise detection section, 2...Port input/output control section, 3...Vector address offset data storage register, 4...Micro sequencer, 5...Micro ROM, 6...Program... Counter, 7... Arithmetic unit, 8... Temporary latch.
Claims (1)
したオフセツト・データを格納するレジスタと、
電源電圧立ち上り後であつて、電源電圧立ち上り
、または、システムリセツト発生、もしくは、割
り込み要求発生にともない発生するベクタ参照ア
ドレス情報に前記レジスタより出力されるオフセ
ツト・データを加算、もしくは、組み合せを行な
い実行アドレスとして出力する手段とを有するこ
とを特徴とするマイクロコンピユータ。 A register that stores offset data input from a specific port when the power supply voltage rises;
After the power supply voltage rises, the offset data output from the register is added or combined with the vector reference address information generated in response to the rise of the power supply voltage, the occurrence of a system reset, or the occurrence of an interrupt request. A microcomputer comprising means for outputting as an address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12540287U JPS6431446U (en) | 1987-08-17 | 1987-08-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12540287U JPS6431446U (en) | 1987-08-17 | 1987-08-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6431446U true JPS6431446U (en) | 1989-02-27 |
Family
ID=31375982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12540287U Pending JPS6431446U (en) | 1987-08-17 | 1987-08-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6431446U (en) |
-
1987
- 1987-08-17 JP JP12540287U patent/JPS6431446U/ja active Pending
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