JPS6431447U - - Google Patents
Info
- Publication number
- JPS6431447U JPS6431447U JP12613387U JP12613387U JPS6431447U JP S6431447 U JPS6431447 U JP S6431447U JP 12613387 U JP12613387 U JP 12613387U JP 12613387 U JP12613387 U JP 12613387U JP S6431447 U JPS6431447 U JP S6431447U
- Authority
- JP
- Japan
- Prior art keywords
- processor
- subroutine
- returns
- input terminal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002265 prevention Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Executing Machine-Instructions (AREA)
- Debugging And Monitoring (AREA)
Description
第１図は本考案の原理ブロツク図、第２図は本
考案の一実施例の回路図、第３図は本考案の動作
説明用タイミングチヤート、第４図はサブルーチ
ンコールの様子を示す概念図、第５図は従来の概
略ブロツク図である。
図において、５はリターン信号（）入力
端子、６はコール信号（）入力端子、７は
リセツト信号（）入力端子、８はデジタル
・シグナル・プロセツサ（ＤＳＰ）、９，１０，
１１はフリツプフロツプ、１２はアラーム信号（
）出力端子、１３は暴走防止回路、１４は
システム全体のリセツト信号入力端子、Ｇ１〜Ｇ
４はゲート、を示す。
Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a timing chart for explaining the operation of the invention, and Fig. 4 is a conceptual diagram showing the state of subroutine calls. , FIG. 5 is a conventional schematic block diagram. In the figure, 5 is a return signal () input terminal, 6 is a call signal () input terminal, 7 is a reset signal () input terminal, 8 is a digital signal processor (DSP), 9, 10,
11 is a flip-flop, 12 is an alarm signal (
) output terminal, 13 is a runaway prevention circuit, 14 is a reset signal input terminal for the entire system, G 1 to G
4 indicates a gate.
Claims (1)
することにより、予め定められている該サブルー
チンのネステイング数に対応したリターン回数を
越えたことを検出して該検出によりプロセツサ８
をリセツトする回路１３よりなり、 該回路１３は該プロセツサ８の内部に設けられ
てなるプロセツサ暴走防止回路。[Claim for Utility Model Registration] By counting the number of returns from a subroutine, it is detected that the number of returns corresponding to the predetermined number of nestings of the subroutine has been exceeded, and upon this detection, the processor 8
The circuit 13 is a processor runaway prevention circuit provided inside the processor 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12613387U JPS6431447U (en) | 1987-08-19 | 1987-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12613387U JPS6431447U (en) | 1987-08-19 | 1987-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6431447U true JPS6431447U (en) | 1989-02-27 |
Family
ID=31377370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12613387U Pending JPS6431447U (en) | 1987-08-19 | 1987-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6431447U (en) |
-
1987
- 1987-08-19 JP JP12613387U patent/JPS6431447U/ja active Pending
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