JPS6431449A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS6431449A
JPS6431449A JP62187944A JP18794487A JPS6431449A JP S6431449 A JPS6431449 A JP S6431449A JP 62187944 A JP62187944 A JP 62187944A JP 18794487 A JP18794487 A JP 18794487A JP S6431449 A JPS6431449 A JP S6431449A
Authority
JP
Japan
Prior art keywords
lead
die pad
solder
chip
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62187944A
Other languages
Japanese (ja)
Inventor
Takahiro Tajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62187944A priority Critical patent/JPS6431449A/en
Publication of JPS6431449A publication Critical patent/JPS6431449A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H10W72/387—Flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent a melted solder from scattering onto a lead frame, the solder from creeping to a die pad lead and to prevent a hanging lead bent part from rising or a die pad from inclining by composing the die pad in a tray-like state capable of containing a semiconductor chip. CONSTITUTION:A die pad 10 is composed in a tray-like state becoming the same plane as the upper end of a lead frame 9, while the frame 9 is bonded to a chip 5 by melting solder 6 on the pad 10, and the upper face of the chip 5 is bonded by a connecting metal fine wiring 7 to the end of an inner lead 11. Accordingly, since the chip 5 is contained in a tray-like die pad, the solder is prevented from flowing, thereby preventing the melted solder from scattering to the surfaces of the frame 9, the lead 11, the hanging lead 12 and creeping on the die pad 2a.
JP62187944A 1987-07-27 1987-07-27 Lead frame for semiconductor device Pending JPS6431449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62187944A JPS6431449A (en) 1987-07-27 1987-07-27 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62187944A JPS6431449A (en) 1987-07-27 1987-07-27 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS6431449A true JPS6431449A (en) 1989-02-01

Family

ID=16214905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62187944A Pending JPS6431449A (en) 1987-07-27 1987-07-27 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS6431449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391916A (en) * 1990-04-06 1995-02-21 Hitachi, Ltd. Resin sealed type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391916A (en) * 1990-04-06 1995-02-21 Hitachi, Ltd. Resin sealed type semiconductor device
US5635756A (en) * 1990-04-06 1997-06-03 Hitachi, Ltd. Semiconductor device, lead frame therefor and memory card to provide a thin structure

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