JPS6431495U - - Google Patents
Info
- Publication number
- JPS6431495U JPS6431495U JP12388987U JP12388987U JPS6431495U JP S6431495 U JPS6431495 U JP S6431495U JP 12388987 U JP12388987 U JP 12388987U JP 12388987 U JP12388987 U JP 12388987U JP S6431495 U JPS6431495 U JP S6431495U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- converts
- conductive
- timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Landscapes
- Emergency Alarm Devices (AREA)
Description
第１図はケースを取り除いた地震センサーの断
面図である。第２図は本考案の地震警報装置の電
気回路図である。
１：地震センサー、２：金属球、３：ベース、
３ａ：絶縁スペーサ、４：カバー、５，５：引出
しリード線、６：電源トランス、７：整流回路、
８：第１タイマー、８ａ：可変抵抗器、９：出力
パルスＴ１、１０，２１，２４：ベース抵抗、１
１，２２：トランジスタ、１２：切換スイツチ、
１３：ゲート電流制限抵抗、１４：制御整流素子
、１５，１５：ＡＣコンセント、１６：ヒユーズ
、１７：バツクアツプ電池、１８：ダイオード、
１９：第２タイマー、２０：出力パルスＴ２、２
３：警報発生回路、２５：ダーリントントランジ
スタ、２６：スピーカ。
Figure 1 is a cross-sectional view of the seismic sensor with the case removed. FIG. 2 is an electrical circuit diagram of the earthquake warning device of the present invention. 1: Earthquake sensor, 2: Metal ball, 3: Base,
3a: Insulating spacer, 4: Cover, 5, 5: Output lead wire, 6: Power transformer, 7: Rectifier circuit,
8: First timer, 8a: Variable resistor, 9: Output pulse T 1 , 10, 21, 24: Base resistor, 1
1, 22: Transistor, 12: Changeover switch,
13: Gate current limiting resistor, 14: Control rectifier, 15, 15: AC outlet, 16: Fuse, 17: Backup battery, 18: Diode,
19: Second timer, 20: Output pulse T 2 , 2
3: Alarm generating circuit, 25: Darlington transistor, 26: Speaker.
Claims (1)
、直流に変換する整流回路と、該整流回路と並列
接続して成るバツクアツプ電池と、自動復帰機能
を有する地震センサーが一瞬閉路することにより
発生するトリガー入力により出力パルスを発生す
る第１及び第２タイマーと、該第１タイマーの出
力パルス幅の間だけ導通状態を保つトランジスタ
及び制御整流素子と、該制御整流素子の導通時に
ＡＣ１００Ｖが供給される複数個のＡＣコンセン
トと、前記第２タイマーの出力パルス幅の間だけ
導通状態を保つトランジスターと、該トランジス
タの導通により前記整流回路からの電圧を電源と
成し警報を発生する警報発生回路と、該警報発生
回路の出力を増幅するトランジスタと、該増幅さ
れた電圧を音に変換するスピーカとより成る地震
警報装置。 A rectifier circuit that converts AC 100V to low voltage with a power transformer and then converts it to DC, a backup battery connected in parallel with the rectifier circuit, and a trigger input generated when an earthquake sensor with an automatic reset function momentarily closes the circuit. first and second timers that generate output pulses; a transistor and a controlled rectifier that remain conductive only during the output pulse width of the first timer; an AC outlet and a transistor that remains conductive only during the output pulse width of the second timer; an alarm generating circuit that generates an alarm by using the voltage from the rectifier circuit as a power source when the transistor is conductive; An earthquake warning device consisting of a transistor that amplifies the output of a circuit and a speaker that converts the amplified voltage into sound.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12388987U JPS6431495U (en) | 1987-08-13 | 1987-08-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12388987U JPS6431495U (en) | 1987-08-13 | 1987-08-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6431495U true JPS6431495U (en) | 1989-02-27 |
Family
ID=31373149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12388987U Pending JPS6431495U (en) | 1987-08-13 | 1987-08-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6431495U (en) |
-
1987
- 1987-08-13 JP JP12388987U patent/JPS6431495U/ja active Pending