JPS6432495A - Non-volatile semiconductor storage device - Google Patents

Non-volatile semiconductor storage device

Info

Publication number
JPS6432495A
JPS6432495A JP18796387A JP18796387A JPS6432495A JP S6432495 A JPS6432495 A JP S6432495A JP 18796387 A JP18796387 A JP 18796387A JP 18796387 A JP18796387 A JP 18796387A JP S6432495 A JPS6432495 A JP S6432495A
Authority
JP
Japan
Prior art keywords
vpp
low level
bit lines
memory
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18796387A
Other languages
Japanese (ja)
Inventor
Yasushi Terada
Kazuo Kobayashi
Takeshi Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18796387A priority Critical patent/JPS6432495A/en
Publication of JPS6432495A publication Critical patent/JPS6432495A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To operate a device with a single supply voltage level by setting non-selected bit lines and word lines to an intermediate voltage value in a write cycle. CONSTITUTION:In the erase cycle ('1' write) of memory transistors TRs Q1 and Q3 connected to a word line WL1, potential levels of bit lines BL1 and BL2 and word lines WL1 and WL2 are set to the low level (OV), the low level, Vpp, and 1/2 Vpp respectively, and electrons are injected from a drain 2 of memory TRs Q1 and Q3 to a floating gate 5 by the tunnel phenomenon to raise the threshold voltage to a positive level. In the write cycle where '1' is written in the memory TR Q1 and '0' is written in the TR Q3, potential levels of bit lines BL1 and BL2 and word lines WL1 and WL2 are set to 1/2 Vpp, Vpp, the low level, and 1/2 Vpp respectively. The tunnel phenomenon is used in the erase cycle as well as the write cycle to eliminate a need of a high current driving capability.
JP18796387A 1987-07-27 1987-07-27 Non-volatile semiconductor storage device Pending JPS6432495A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18796387A JPS6432495A (en) 1987-07-27 1987-07-27 Non-volatile semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18796387A JPS6432495A (en) 1987-07-27 1987-07-27 Non-volatile semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6432495A true JPS6432495A (en) 1989-02-02

Family

ID=16215223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18796387A Pending JPS6432495A (en) 1987-07-27 1987-07-27 Non-volatile semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6432495A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58162952A (en) * 1982-03-24 1983-09-27 Dainippon Printing Co Ltd trimming scanner
JPH03135560A (en) * 1990-06-02 1991-06-10 Dainippon Printing Co Ltd Trimming device of scanner
WO1992005560A1 (en) * 1990-09-25 1992-04-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US6519183B2 (en) * 2000-07-18 2003-02-11 Stmicroelectronics S.R.L. Method and a circuit structure for modifying the threshold voltages of non-volatile memory cells

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58162952A (en) * 1982-03-24 1983-09-27 Dainippon Printing Co Ltd trimming scanner
JPH03135560A (en) * 1990-06-02 1991-06-10 Dainippon Printing Co Ltd Trimming device of scanner
WO1992005560A1 (en) * 1990-09-25 1992-04-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US6519183B2 (en) * 2000-07-18 2003-02-11 Stmicroelectronics S.R.L. Method and a circuit structure for modifying the threshold voltages of non-volatile memory cells

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