JPS6432599U - - Google Patents
Info
- Publication number
- JPS6432599U JPS6432599U JP12680487U JP12680487U JPS6432599U JP S6432599 U JPS6432599 U JP S6432599U JP 12680487 U JP12680487 U JP 12680487U JP 12680487 U JP12680487 U JP 12680487U JP S6432599 U JPS6432599 U JP S6432599U
- Authority
- JP
- Japan
- Prior art keywords
- output
- reverberation adding
- sets
- reverberation
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 1
Description
第１図は本考案の一実施例に係る残響付加装置
の原理ブロツク図、第２図は本考案の一実施例に
係る残響付加装置の具体的構成を示すブロツク図
、第３図は第２図の音色パラメータメモリ２５の
内部構成を示す図、第４図は第２図の音色パラメ
ータメモリ２６の内部構成を示す図、第５図は第
２図の波形データメモリの内部構成を示す図、第
６図は残響付加装置の処理動作を示すフローチヤ
ート、第７図は第２図の波形データメモリの書き
込みアドレスの説明図、第８図は従来のステレオ
の残響付加装置のブロツク図、第９図は第８図の
残響付加回路の一例を示すブロツク図である。
１１……残響付加回路、１２……ステレオ化回
路、１３−１〜１３〜６……遅延回路、１４−１
〜１４−６……乗算回路、１５−１〜１５−６…
…加算回路、１７，１８……乗算回路、１９，２
０……加算回路、２１……プログラムメモリ、２
５，２６……音色パラメータメモリ、２９……演
算回路、３０……乗算回路、３３……波形データ
メモリ。
FIG. 1 is a principle block diagram of a reverberation adding device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of a reverberation adding device according to an embodiment of the present invention, and FIG. 4 is a diagram showing the internal configuration of the timbre parameter memory 25 in FIG. 2, FIG. 5 is a diagram showing the internal configuration of the waveform data memory 26 in FIG. 2, FIG. 6 is a flowchart showing the processing operation of the reverberation adding device, FIG. 7 is an explanatory diagram of the write address of the waveform data memory in FIG. 2, FIG. 8 is a block diagram of the conventional stereo reverberation adding device, and FIG. This figure is a block diagram showing an example of the reverberation adding circuit of FIG. 8. 11...Reverberation addition circuit, 12...Stereo conversion circuit, 13-1 to 13-6...Delay circuit, 14-1
~14-6...multiplication circuit, 15-1~15-6...
... Addition circuit, 17, 18 ... Multiplication circuit, 19, 2
0...Addition circuit, 21...Program memory, 2
5, 26... Tone parameter memory, 29... Arithmetic circuit, 30... Multiplication circuit, 33... Waveform data memory.
Claims (1)
りなる入力側の残響付加手段と、 該残響付加手段の出力を共通の入力とする２組
の遅延手段と、 前記２組の遅延手段の出力を各々独立して出力
する出力手段と、 を有し、前記出力手段よりステレオ出力を得る
ことを特徴とする残響付加装置。[Claims for Utility Model Registration] Reverberation adding means on the input side consisting of a plurality of delaying means that commonly receive a monaural signal; two sets of delaying means whose common input is the output of the reverberation adding means; and the two sets. 1. A reverberation adding device comprising: output means for independently outputting the outputs of the delay means, and a stereo output is obtained from the output means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987126804U JP2542616Y2 (en) | 1987-08-20 | 1987-08-20 | Reverberation device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987126804U JP2542616Y2 (en) | 1987-08-20 | 1987-08-20 | Reverberation device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6432599U true JPS6432599U (en) | 1989-03-01 |
| JP2542616Y2 JP2542616Y2 (en) | 1997-07-30 |
Family
ID=31378654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987126804U Expired - Lifetime JP2542616Y2 (en) | 1987-08-20 | 1987-08-20 | Reverberation device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2542616Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2022049761A1 (en) * | 2020-09-07 | 2022-03-10 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57143800U (en) * | 1981-03-05 | 1982-09-09 | ||
| JPS5814898A (en) * | 1981-07-20 | 1983-01-27 | ヤマハ株式会社 | Reverberation adding apparatus |
| JPS6051894A (en) * | 1983-08-31 | 1985-03-23 | ヤマハ株式会社 | Reverberation adder |
| JPS61195699U (en) * | 1985-05-28 | 1986-12-05 |
-
1987
- 1987-08-20 JP JP1987126804U patent/JP2542616Y2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57143800U (en) * | 1981-03-05 | 1982-09-09 | ||
| JPS5814898A (en) * | 1981-07-20 | 1983-01-27 | ヤマハ株式会社 | Reverberation adding apparatus |
| JPS6051894A (en) * | 1983-08-31 | 1985-03-23 | ヤマハ株式会社 | Reverberation adder |
| JPS61195699U (en) * | 1985-05-28 | 1986-12-05 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2022049761A1 (en) * | 2020-09-07 | 2022-03-10 | ||
| WO2022049761A1 (en) * | 2020-09-07 | 2022-03-10 | ＡｌｐｈａＴｈｅｔａ株式会社 | Audio signal processing device, audio signal processing method, and program |
| US12379892B2 (en) | 2020-09-07 | 2025-08-05 | Alphatheta Corporation | Audio signal processing device, audio signal processing method, and program |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2542616Y2 (en) | 1997-07-30 |
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