JPS643261U - - Google Patents
Info
- Publication number
- JPS643261U JPS643261U JP9502187U JP9502187U JPS643261U JP S643261 U JPS643261 U JP S643261U JP 9502187 U JP9502187 U JP 9502187U JP 9502187 U JP9502187 U JP 9502187U JP S643261 U JPS643261 U JP S643261U
- Authority
- JP
- Japan
- Prior art keywords
- switching element
- output
- integration
- circuit
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は本考案の一実施例の同期信号生成回路
の回路図、第２図ａ〜ｄは第１図の動作説明のた
めの波形図、第３図は第１図に示した同期信号生
成回路を組み込んだＣＲＴ表示装置の回路図であ
る。
１……同期信号入力端子、２……トランジスタ
、３……プルアツプ抵抗、４……積分回路、５…
…抵抗、６……コンデンサ、７……インバータ、
８……ナンドゲート。
FIG. 1 is a circuit diagram of a synchronizing signal generation circuit according to an embodiment of the present invention, FIGS. 2 a to d are waveform diagrams for explaining the operation of FIG. 1, and FIG. 3 is a synchronizing signal shown in FIG. 1. 1 is a circuit diagram of a CRT display device incorporating a generation circuit. 1...Synchronization signal input terminal, 2...Transistor, 3...Pull-up resistor, 4...Integrator circuit, 5...
...Resistor, 6...Capacitor, 7...Inverter,
8...Nand Gate.
Claims (1)
パルスによりスイツチングするスイツチング素子
と、一方の入力端子に該スイツチング素子の出力
をそのまま入力し、他方の入力端子に該スイツチ
ング素子の出力を積分回路を介して入力し、出力
端子に該積分回路の積分定数に応じた幅のパルス
を出力するゲートとで構成したことを特徴とする
同期信号生成回路。 (2) 上記積分回路の積分定数を、水平同期信号
用と垂直同期信号用とで異ならせたことを特徴と
する実用新案登録請求の範囲第１項記載の実用新
案登録請求の範囲第１項記載の同期信号生成回路
。[Claims for Utility Model Registration] (1) A switching element that switches according to a retrace pulse obtained by a deflection means of a CRT display device, and the output of the switching element is inputted as is to one input terminal, and the output of the switching element is inputted as is to the other input terminal. 1. A synchronization signal generation circuit comprising a gate that inputs the output of the switching element via an integration circuit and outputs a pulse having a width corresponding to an integration constant of the integration circuit to an output terminal. (2) Utility model registration claim 1, characterized in that the integration constant of the integrating circuit is different for horizontal synchronization signals and vertical synchronization signals. The synchronization signal generation circuit described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9502187U JPS643261U (en) | 1987-06-20 | 1987-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9502187U JPS643261U (en) | 1987-06-20 | 1987-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS643261U true JPS643261U (en) | 1989-01-10 |
Family
ID=31319632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9502187U Pending JPS643261U (en) | 1987-06-20 | 1987-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS643261U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5229114A (en) * | 1975-08-30 | 1977-03-04 | Toshiba Corp | Synchronous circuit |
| JPS59126372A (en) * | 1983-01-06 | 1984-07-20 | Matsushita Electric Ind Co Ltd | Noise removal device |
-
1987
- 1987-06-20 JP JP9502187U patent/JPS643261U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5229114A (en) * | 1975-08-30 | 1977-03-04 | Toshiba Corp | Synchronous circuit |
| JPS59126372A (en) * | 1983-01-06 | 1984-07-20 | Matsushita Electric Ind Co Ltd | Noise removal device |
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