JPS643275U - - Google Patents

Info

Publication number
JPS643275U
JPS643275U JP9478187U JP9478187U JPS643275U JP S643275 U JPS643275 U JP S643275U JP 9478187 U JP9478187 U JP 9478187U JP 9478187 U JP9478187 U JP 9478187U JP S643275 U JPS643275 U JP S643275U
Authority
JP
Japan
Prior art keywords
switching circuit
audio
channels
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9478187U
Other languages
Japanese (ja)
Other versions
JPH0523027Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9478187U priority Critical patent/JPH0523027Y2/ja
Publication of JPS643275U publication Critical patent/JPS643275U/ja
Application granted granted Critical
Publication of JPH0523027Y2 publication Critical patent/JPH0523027Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Television Receiver Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す図、第2図は
第2入力切換回路18の入出力信号の関係を示す
図である。第3図は改良例を示す図である。第4
図は従来例を示す図である。第5図は音声多重デ
コーダの出力を示す図である。 12……音声多重デコーダ、イ……制御信号、
MS……出力モード設定スイツチ(出力モード
設定手段)、16L,16R……ピンジヤツク(
ライン入力端子)、14……第1入力切換回路、
18……第2入力切換回路、22……記録再生回
路、24……出力切換回路、MS……切換設定
手段。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between input and output signals of the second input switching circuit 18. FIG. 3 is a diagram showing an improved example. Fourth
The figure shows a conventional example. FIG. 5 is a diagram showing the output of the audio multiplex decoder. 12... Audio multiplex decoder, a... Control signal,
MS 4 ... Output mode setting switch (output mode setting means), 16L, 16R... Pin jack (
line input terminal), 14...first input switching circuit,
18... Second input switching circuit, 22... Recording and reproducing circuit, 24... Output switching circuit, MS 5 ... Switching setting means.

Claims (1)

【実用新案登録請求の範囲】 音声多重デコーダよりステレオ、モノラル或い
は2重音声のいずれかの2チヤンネル音声信号を
選択的に出力せしめるための制御信号を出力する
出力モード設定手段と、 前記音声多重デコーダからの2チヤンネルの音
声信号とライン入力端子からの2チヤンネルの音
声信号を選択出力する第1入力切換回路と、 この第1入力切換回路からの2チヤンネルの音
声信号を夫々選択して2チヤンネルの音声信号を
出力する第2入力切換回路と、 この第2入力切換回路からの2チヤンネルの音
声信号を記録再生する記録再生回路と、 この記録再生回路より出力される2チヤンネル
の音声信号を夫々選択して2チヤンネルの音声信
号を出力する出力切換回路とを、備えるビデオテ
ープレコーダの信号切換回路に於いて、 前記出力モード設定手段がデユアル用の前記制
御信号を出力し且つ前記第1入力切換回路が前記
音声多重デコーダからの2チヤンネルの音声信号
を選択出力している時に、前記第2入力切換回路
と前記出力切換回路とを関連して制御する切換設
定手段を、 備えることを特徴とするビデオテープレコーダ
の信号切換回路。
[Claims for Utility Model Registration] Output mode setting means for outputting a control signal for selectively outputting a two-channel audio signal of stereo, monaural, or dual audio from an audio multiplex decoder; and the audio multiplex decoder. A first input switching circuit selectively outputs two channels of audio signals from the line input terminal and two channels of audio signals from the line input terminal; A second input switching circuit that outputs an audio signal, a recording and reproducing circuit that records and reproduces two channels of audio signals from this second input switching circuit, and selects each of the two channels of audio signals output from this recording and reproducing circuit. and an output switching circuit for outputting a two-channel audio signal, wherein the output mode setting means outputs the control signal for dual and the first input switching circuit outputs the dual-channel audio signal. The video apparatus is characterized in that it comprises switching setting means for controlling the second input switching circuit and the output switching circuit in conjunction with each other when the audio signal of two channels from the audio multiplex decoder is selectively output. Tape recorder signal switching circuit.
JP9478187U 1987-06-19 1987-06-19 Expired - Lifetime JPH0523027Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9478187U JPH0523027Y2 (en) 1987-06-19 1987-06-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9478187U JPH0523027Y2 (en) 1987-06-19 1987-06-19

Publications (2)

Publication Number Publication Date
JPS643275U true JPS643275U (en) 1989-01-10
JPH0523027Y2 JPH0523027Y2 (en) 1993-06-14

Family

ID=31319355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9478187U Expired - Lifetime JPH0523027Y2 (en) 1987-06-19 1987-06-19

Country Status (1)

Country Link
JP (1) JPH0523027Y2 (en)

Also Published As

Publication number Publication date
JPH0523027Y2 (en) 1993-06-14

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