JPS643337U - - Google Patents
Info
- Publication number
- JPS643337U JPS643337U JP9597387U JP9597387U JPS643337U JP S643337 U JPS643337 U JP S643337U JP 9597387 U JP9597387 U JP 9597387U JP 9597387 U JP9597387 U JP 9597387U JP S643337 U JPS643337 U JP S643337U
- Authority
- JP
- Japan
- Prior art keywords
- coincidence
- bit counter
- count
- output
- detection circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Logic Circuits (AREA)
Description
第１図から第３図は本考案の複数系統一致回路
の一実施例を示し、第１図は全体構成を示すブロ
ツク図、第２図は一致検出回路の一例を示す論理
回路図、第３図は本実施例によつて発せられる各
パルスの状態を示す線図、第４図は従来の複数系
統一致回路が適用されているワイヤドツトヘツド
部分を示す側面図、第５図は従来の複数系統一致
回路を示すブロツク図である。
１……ワイヤドツトヘツド、５１〜５ｐ……ワ
イヤ、８……印字素子駆動部、１１……ｎビツト
カウンタ、１２１〜１２ｐ……一致検出回路、１
３１〜１３ｐ……カウント情報、１４１〜１４ｎ
……排他的論理和回路、１５……多入力ＯＲ回路
。
1 to 3 show an embodiment of the multi-system matching circuit of the present invention, FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is a logic circuit diagram showing an example of the matching detection circuit, and FIG. The figure is a diagram showing the state of each pulse emitted by this embodiment, FIG. 4 is a side view showing the wire dot head portion to which a conventional multiple system matching circuit is applied, and FIG. FIG. 3 is a block diagram showing a system matching circuit. DESCRIPTION OF SYMBOLS 1... Wire dot head, 5 1 to 5p... Wire, 8... Print element drive section, 11... n bit counter, 12 1 to 12p... Coincidence detection circuit, 1
3 1 to 13p...Count information, 14 1 to 14n
...Exclusive OR circuit, 15...Multi-input OR circuit.
Claims (1)
ントを順に出力するｎビツトカウンタと、このｎ
ビツトカウンタの出力側に並列に接続されている
複数の一致検出回路であつて、それぞれに入力さ
れるカウント情報と前記ｎビツトカウンタの出力
であるカウント数とが一致している場合に一致出
力を発する複数の一致検出回路とを有する複数系
統一致回路。 An n-bit counter that sequentially outputs a count of n bits based on input from a clock;
A plurality of coincidence detection circuits connected in parallel to the output side of a bit counter, which output a coincidence when the count information input to each one matches the count number output from the n-bit counter. A plurality of system coincidence circuits having a plurality of coincidence detection circuits that emit signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9597387U JPH0533076Y2 (en) | 1987-06-24 | 1987-06-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9597387U JPH0533076Y2 (en) | 1987-06-24 | 1987-06-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS643337U true JPS643337U (en) | 1989-01-10 |
| JPH0533076Y2 JPH0533076Y2 (en) | 1993-08-24 |
Family
ID=31320753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9597387U Expired - Lifetime JPH0533076Y2 (en) | 1987-06-24 | 1987-06-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0533076Y2 (en) |
-
1987
- 1987-06-24 JP JP9597387U patent/JPH0533076Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0533076Y2 (en) | 1993-08-24 |
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