JPS6433650A - Data transfer circuit - Google Patents

Data transfer circuit

Info

Publication number
JPS6433650A
JPS6433650A JP62190758A JP19075887A JPS6433650A JP S6433650 A JPS6433650 A JP S6433650A JP 62190758 A JP62190758 A JP 62190758A JP 19075887 A JP19075887 A JP 19075887A JP S6433650 A JPS6433650 A JP S6433650A
Authority
JP
Japan
Prior art keywords
parity
circuit
data
output
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62190758A
Other languages
Japanese (ja)
Inventor
Jun Kanatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62190758A priority Critical patent/JPS6433650A/en
Publication of JPS6433650A publication Critical patent/JPS6433650A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To decrease the number of circuits for a data transfer circuit by supplying a parity generated via a data bus at the transfer of data with no parity after checking the presence of a parity so that a parity generating circuit is not required for each output circuits. CONSTITUTION:A parity presence pointing circuit 6 checks the presence of the parity of the data to be transferred. When the absence of the parity is confirmed, an output circuit 5 delivers data to a data bus signal line 101 and a parity generating circuit 3 produces a parity from the data on the line 101 to supply this parity to a switching circuit 4. The circuit 4 selects the output of the circuit 3 and supplies this to an input latch circuit 1. Thus the correct parity data is outputted from the circuit 1 and those data including the parity bits are transferred as they are. Thus it is not required to add a parity generating circuit to each output circuit and therefore the circuit hardware quantity is reduced.
JP62190758A 1987-07-30 1987-07-30 Data transfer circuit Pending JPS6433650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62190758A JPS6433650A (en) 1987-07-30 1987-07-30 Data transfer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62190758A JPS6433650A (en) 1987-07-30 1987-07-30 Data transfer circuit

Publications (1)

Publication Number Publication Date
JPS6433650A true JPS6433650A (en) 1989-02-03

Family

ID=16263242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62190758A Pending JPS6433650A (en) 1987-07-30 1987-07-30 Data transfer circuit

Country Status (1)

Country Link
JP (1) JPS6433650A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007262964A (en) * 2006-03-28 2007-10-11 Isuzu Motors Ltd Turbocharger control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007262964A (en) * 2006-03-28 2007-10-11 Isuzu Motors Ltd Turbocharger control device

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