JPS6433752U - - Google Patents

Info

Publication number
JPS6433752U
JPS6433752U JP1987127769U JP12776987U JPS6433752U JP S6433752 U JPS6433752 U JP S6433752U JP 1987127769 U JP1987127769 U JP 1987127769U JP 12776987 U JP12776987 U JP 12776987U JP S6433752 U JPS6433752 U JP S6433752U
Authority
JP
Japan
Prior art keywords
conductive pattern
wiring board
lead frame
deposited
feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987127769U
Other languages
Japanese (ja)
Other versions
JPH0735404Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987127769U priority Critical patent/JPH0735404Y2/en
Publication of JPS6433752U publication Critical patent/JPS6433752U/ja
Application granted granted Critical
Publication of JPH0735404Y2 publication Critical patent/JPH0735404Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係る半導体装置の一実施例を
示す組立分解斜視図、第２図は第１図装置の組立
完了斜視図、第３図は第２図のＡ矢視図、第４図
及び第５図はそれぞれ本考案の他の実施例を示す
部分斜視図である。第６図はハイブリツドＩＣの
従来例を示す組立分解斜視図、第７図は第６図装
置の組立完了斜視図、第８図は第７図のＢ―Ｂ線
に沿う断面図である。 ２０……リードフレーム、２１……一部（吊り
ピン）、２５……配線基板、２６……導電パター
ン、２７……電子部品。 FIG. 1 is an exploded perspective view showing an embodiment of the semiconductor device according to the present invention, FIG. 2 is a perspective view of the device shown in FIG. 1 after assembly, FIG. 5 and 5 are partial perspective views showing other embodiments of the present invention, respectively. FIG. 6 is an exploded perspective view showing a conventional example of a hybrid IC, FIG. 7 is a perspective view of the device shown in FIG. 6 after assembly, and FIG. 8 is a sectional view taken along line BB in FIG. 20... Lead frame, 21... Part (hanging pin), 25... Wiring board, 26... Conductive pattern, 27... Electronic component.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 導電パターンを被着形成すると共に、この導電
パターン上に複数の半導体ペレツトを含む電子部
品をマウントした絶縁性の配線基板を、金属製リ
ードフレームの一部に直接的に橋架支持したこと
を特徴とする半導体装置。 A feature is that an insulating wiring board on which a conductive pattern is deposited and electronic components including a plurality of semiconductor pellets are mounted on the conductive pattern is directly bridge-supported on a part of the metal lead frame. semiconductor devices.
JP1987127769U 1987-08-21 1987-08-21 Semiconductor device Expired - Lifetime JPH0735404Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987127769U JPH0735404Y2 (en) 1987-08-21 1987-08-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987127769U JPH0735404Y2 (en) 1987-08-21 1987-08-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6433752U true JPS6433752U (en) 1989-03-02
JPH0735404Y2 JPH0735404Y2 (en) 1995-08-09

Family

ID=31380493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987127769U Expired - Lifetime JPH0735404Y2 (en) 1987-08-21 1987-08-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0735404Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61136249A (en) * 1984-12-06 1986-06-24 Nec Kansai Ltd Hybrid ic

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61136249A (en) * 1984-12-06 1986-06-24 Nec Kansai Ltd Hybrid ic

Also Published As

Publication number Publication date
JPH0735404Y2 (en) 1995-08-09

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