JPS6433793A - Refresh controller - Google Patents

Refresh controller

Info

Publication number
JPS6433793A
JPS6433793A JP62188756A JP18875687A JPS6433793A JP S6433793 A JPS6433793 A JP S6433793A JP 62188756 A JP62188756 A JP 62188756A JP 18875687 A JP18875687 A JP 18875687A JP S6433793 A JPS6433793 A JP S6433793A
Authority
JP
Japan
Prior art keywords
address
dram
refresh
sram
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62188756A
Other languages
Japanese (ja)
Inventor
Kazuyuki Aizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62188756A priority Critical patent/JPS6433793A/en
Publication of JPS6433793A publication Critical patent/JPS6433793A/en
Pending legal-status Critical Current

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  • Dram (AREA)

Abstract

PURPOSE:To improve the access efficiency of a DRAM by a CPU or the like by executing the refresh of the DRAM only to an address requiring the refresh and shortening a time required for the refresh or the DRAM. CONSTITUTION:At the time of making access to the DRAM 6 by the CPU 2, '1' is stored in the data area of the address of a SRAM 16 corresponding to the access of the DRAM 6, the contents of the data area of the SRAM 16 corresponding to an address formed from an address counter 12 for every refresh cycle are read, and when the read data is '1', a REFRQ # signal output from a controller 17 is not validated, so that the address of the DRAM 6 corresponding to this address is not refreshed. When the data read from the SRAM 16 is not '1', the REFRQ # signal from the controller 17 is validated, the address of the DRAM 6 corresponding to this address is refreshed.
JP62188756A 1987-07-30 1987-07-30 Refresh controller Pending JPS6433793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62188756A JPS6433793A (en) 1987-07-30 1987-07-30 Refresh controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62188756A JPS6433793A (en) 1987-07-30 1987-07-30 Refresh controller

Publications (1)

Publication Number Publication Date
JPS6433793A true JPS6433793A (en) 1989-02-03

Family

ID=16229220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62188756A Pending JPS6433793A (en) 1987-07-30 1987-07-30 Refresh controller

Country Status (1)

Country Link
JP (1) JPS6433793A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120731A (en) * 1976-04-05 1977-10-11 Nec Corp Refresh control circuit
JPS52130535A (en) * 1976-04-27 1977-11-01 Nippon Telegr & Teleph Corp <Ntt> Refresh control system of memory unit
JPS58215790A (en) * 1982-06-07 1983-12-15 Hitachi Ltd Refresh circuit of dynamic ram
JPS6032200A (en) * 1983-08-02 1985-02-19 Seikosha Co Ltd Refresh control circuit of dynamic memory
JPS6120295A (en) * 1984-07-05 1986-01-29 Nec Corp Integrated circuit for address control
JPS6231091A (en) * 1985-08-02 1987-02-10 Nec Corp System for controlling refresh of dynamic memory

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120731A (en) * 1976-04-05 1977-10-11 Nec Corp Refresh control circuit
JPS52130535A (en) * 1976-04-27 1977-11-01 Nippon Telegr & Teleph Corp <Ntt> Refresh control system of memory unit
JPS58215790A (en) * 1982-06-07 1983-12-15 Hitachi Ltd Refresh circuit of dynamic ram
JPS6032200A (en) * 1983-08-02 1985-02-19 Seikosha Co Ltd Refresh control circuit of dynamic memory
JPS6120295A (en) * 1984-07-05 1986-01-29 Nec Corp Integrated circuit for address control
JPS6231091A (en) * 1985-08-02 1987-02-10 Nec Corp System for controlling refresh of dynamic memory

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