JPS6436363A - System for making access to dual port memory - Google Patents

System for making access to dual port memory

Info

Publication number
JPS6436363A
JPS6436363A JP19189287A JP19189287A JPS6436363A JP S6436363 A JPS6436363 A JP S6436363A JP 19189287 A JP19189287 A JP 19189287A JP 19189287 A JP19189287 A JP 19189287A JP S6436363 A JPS6436363 A JP S6436363A
Authority
JP
Japan
Prior art keywords
access
page
cpu12
slave
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19189287A
Other languages
Japanese (ja)
Inventor
Eiichi Seto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP19189287A priority Critical patent/JPS6436363A/en
Publication of JPS6436363A publication Critical patent/JPS6436363A/en
Pending legal-status Critical Current

Links

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  • Multi Processors (AREA)

Abstract

PURPOSE:To simplify an access arbitration means and to improve a memory cycle time and the performance of a throughput, by dividing a memory into two pages, and enabling a remaining page to be accessed by reading a status in making access by a master CPU by a slave CPU. CONSTITUTION:The titled system is constituted so that the memory 11 is divided into two pages and both CPUs 12 and 13 can make access to them at every page, and a status register 18 which stores the fact of making access of the CPU12 including page information from the CPU12 out of the CPUs 1 and 13 and supplies the information to another slave CPU13 is provided. And the system is constituted so that the slave CPU13 can make access to the remaining page from the page information while the master CPU12 makes access and access arbitration can be performed only by the write and the read of status information, and simultaneous access by the master CPU12 and the slave CPU13 at every page can be performed. In such a way, it is possible to perform a fast and efficient data processing while keeping the easiness of the access arbitration.
JP19189287A 1987-07-31 1987-07-31 System for making access to dual port memory Pending JPS6436363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19189287A JPS6436363A (en) 1987-07-31 1987-07-31 System for making access to dual port memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19189287A JPS6436363A (en) 1987-07-31 1987-07-31 System for making access to dual port memory

Publications (1)

Publication Number Publication Date
JPS6436363A true JPS6436363A (en) 1989-02-07

Family

ID=16282186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19189287A Pending JPS6436363A (en) 1987-07-31 1987-07-31 System for making access to dual port memory

Country Status (1)

Country Link
JP (1) JPS6436363A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991018346A1 (en) * 1990-05-14 1991-11-28 Kabushiki Kaisha Komatsu Seisakusho Device for transmitting a synchronous data
JP2010009580A (en) * 2008-03-31 2010-01-14 Intel Corp Partition-free multisocket memory system architecture
JP2012108886A (en) * 2010-11-16 2012-06-07 Micron Technology Inc Multi-channel memory with embedded channel selection

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991018346A1 (en) * 1990-05-14 1991-11-28 Kabushiki Kaisha Komatsu Seisakusho Device for transmitting a synchronous data
JP2010009580A (en) * 2008-03-31 2010-01-14 Intel Corp Partition-free multisocket memory system architecture
JP2013178823A (en) * 2008-03-31 2013-09-09 Intel Corp Partition-free multi-socket memory system architecture
US8605099B2 (en) 2008-03-31 2013-12-10 Intel Corporation Partition-free multi-socket memory system architecture
JP2012108886A (en) * 2010-11-16 2012-06-07 Micron Technology Inc Multi-channel memory with embedded channel selection

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