JPS6437063U - - Google Patents
Info
- Publication number
- JPS6437063U JPS6437063U JP1987131720U JP13172087U JPS6437063U JP S6437063 U JPS6437063 U JP S6437063U JP 1987131720 U JP1987131720 U JP 1987131720U JP 13172087 U JP13172087 U JP 13172087U JP S6437063 U JPS6437063 U JP S6437063U
- Authority
- JP
- Japan
- Prior art keywords
- photocoupler
- package structure
- power control
- heat sink
- optical transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987131720U JPS6437063U (mo) | 1987-08-28 | 1987-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987131720U JPS6437063U (mo) | 1987-08-28 | 1987-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6437063U true JPS6437063U (mo) | 1989-03-06 |
Family
ID=31388047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987131720U Pending JPS6437063U (mo) | 1987-08-28 | 1987-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6437063U (mo) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57118680A (en) * | 1981-01-16 | 1982-07-23 | Toshiba Corp | Photocoupled semiconductor device |
-
1987
- 1987-08-28 JP JP1987131720U patent/JPS6437063U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57118680A (en) * | 1981-01-16 | 1982-07-23 | Toshiba Corp | Photocoupled semiconductor device |