JPS6437133A - Optical reception circuit - Google Patents

Optical reception circuit

Info

Publication number
JPS6437133A
JPS6437133A JP62191523A JP19152387A JPS6437133A JP S6437133 A JPS6437133 A JP S6437133A JP 62191523 A JP62191523 A JP 62191523A JP 19152387 A JP19152387 A JP 19152387A JP S6437133 A JPS6437133 A JP S6437133A
Authority
JP
Japan
Prior art keywords
circuit
proportional
output
apd
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62191523A
Other languages
Japanese (ja)
Inventor
Soji Horikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62191523A priority Critical patent/JPS6437133A/en
Publication of JPS6437133A publication Critical patent/JPS6437133A/en
Pending legal-status Critical Current

Links

Landscapes

  • Optical Communication System (AREA)

Abstract

PURPOSE:To stably perform the automatic gain control by changing the reverse bias voltage of a photoelectric transducer in accordance with a signal obtained by inputting a voltage proportional to the DC component of the photoelectric transducer output to a circuit which has a saturation input/output characteristic. CONSTITUTION:The output of an avalanche photodiode (APD) 1 being photoelectric conversion element is inputted to a DC level detecting circuit 5 through a preamplifier 2, and the signal proportional to the DC component is detected. This signal is applied to DC/DC converter 7 through a nonlinear circuit 6 to control a reverse bias voltage (Va) applied to the APD 1. Thus, an amplification factor M of the APD 1 is changed in accordance with the voltage Va to control the output of the circuit 5 to a fixed value. Since the input/output characteristic of the circuit 6 is proportional to Va/M, the nonlinear change of the overall DC open loop gain which is accompanied with the variance of the light reception level and is proportional to M/Va is cancelled to stably perform automatic gain control.
JP62191523A 1987-08-01 1987-08-01 Optical reception circuit Pending JPS6437133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62191523A JPS6437133A (en) 1987-08-01 1987-08-01 Optical reception circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62191523A JPS6437133A (en) 1987-08-01 1987-08-01 Optical reception circuit

Publications (1)

Publication Number Publication Date
JPS6437133A true JPS6437133A (en) 1989-02-07

Family

ID=16276080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62191523A Pending JPS6437133A (en) 1987-08-01 1987-08-01 Optical reception circuit

Country Status (1)

Country Link
JP (1) JPS6437133A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013076769A1 (en) * 2011-11-24 2013-05-30 三菱電機株式会社 Optical range finder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013076769A1 (en) * 2011-11-24 2013-05-30 三菱電機株式会社 Optical range finder

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