JPS643735A - Control system - Google Patents

Control system

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Publication number
JPS643735A
JPS643735A JP15794487A JP15794487A JPS643735A JP S643735 A JPS643735 A JP S643735A JP 15794487 A JP15794487 A JP 15794487A JP 15794487 A JP15794487 A JP 15794487A JP S643735 A JPS643735 A JP S643735A
Authority
JP
Japan
Prior art keywords
number information
edition number
information
coincidence
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15794487A
Other languages
Japanese (ja)
Inventor
Kiyoshi Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15794487A priority Critical patent/JPS643735A/en
Publication of JPS643735A publication Critical patent/JPS643735A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To confirm the coincidence of contents of microprogram P of plural controllers sharing a device to be controlled in a short time and to prevent the fault caused by the disturbance of the control information, by performing comparison of the edition number information among those microprograms muP. CONSTITUTION:The edition number information of the muP are read out of a microprogram memory part 14 and the systems A and B of an information memory part 15 are written into addresses 0 and 1 respectively when the power supply is applied to a microprocessor 13 of the system A for initialization. Then the output of an FF 16 of the system B is checked and decided as 0. Thus an FF 16 of the system A is set at 1 and the operation is started. When the power supply is applied to the system B for initialization, the same operation as that of the system A is carried out. A processor 13 of the system B compares the edition number information on the P of the system A stored in an address 0 of the part 15 of the system A with the maximum address of the part 14 of the system B or the edition number information on the address 1 of the part 15. Then the coincidence is obtained from this comparison, the contents of the part 15 of the system A are copied to the part 15 of the system B. Then the operation is started after setting the FF 16 at 1. When no coincidence is obtained, the processor 13 of the system B erites the fault information to the specific areas of both parts 15 to stop the operation.
JP15794487A 1987-06-26 1987-06-26 Control system Pending JPS643735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15794487A JPS643735A (en) 1987-06-26 1987-06-26 Control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15794487A JPS643735A (en) 1987-06-26 1987-06-26 Control system

Publications (1)

Publication Number Publication Date
JPS643735A true JPS643735A (en) 1989-01-09

Family

ID=15660882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15794487A Pending JPS643735A (en) 1987-06-26 1987-06-26 Control system

Country Status (1)

Country Link
JP (1) JPS643735A (en)

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