JPS643745A - Emulation system - Google Patents

Emulation system

Info

Publication number
JPS643745A
JPS643745A JP62157709A JP15770987A JPS643745A JP S643745 A JPS643745 A JP S643745A JP 62157709 A JP62157709 A JP 62157709A JP 15770987 A JP15770987 A JP 15770987A JP S643745 A JPS643745 A JP S643745A
Authority
JP
Japan
Prior art keywords
circuit
hmuc4
osct
tmuc
dividing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62157709A
Other languages
Japanese (ja)
Inventor
Shin Matsuoka
Giichi Aoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP62157709A priority Critical patent/JPS643745A/en
Publication of JPS643745A publication Critical patent/JPS643745A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To completely support the working frequency of an evaluating microcomputer (HmuC) by setting a circuit which oscillates by an oscillator for a target microcomputer (TmuC) at a place adjacent to a mounting area of the TmuC and producing a reference clock of the HmuC from the output of said circuit. CONSTITUTION:A connection terminal EXTALt of a TmuC mounting area 7 connected with an oscillator OSCLTR of a user real device 1 is provided on a plug 6 together with an oscillation circuit OSCt connected to the terminal XTALt. Then an evaluation action mode setting signal Vpp is supplied to an evaluating action mode setting external terminal PnS of an HmuC4 and this HXC4 is set under an evaluation mode. At the same time, the dividing ratio of a dividing circuit CDe is set again. Then the circuit OSCt is oscillated by the OSCLTR and the output frequency of the OSCt is divided into 1/2 by a dividing circuit CDt. A clock signal CLKt is supplied to an external terminal EXTALe of the HmuC4. The circuit CDe of the HmuC4 divides the frequency in the set dividing ratio for production of a reference clock of the HmuC4.
JP62157709A 1987-06-26 1987-06-26 Emulation system Pending JPS643745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62157709A JPS643745A (en) 1987-06-26 1987-06-26 Emulation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62157709A JPS643745A (en) 1987-06-26 1987-06-26 Emulation system

Publications (1)

Publication Number Publication Date
JPS643745A true JPS643745A (en) 1989-01-09

Family

ID=15655658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62157709A Pending JPS643745A (en) 1987-06-26 1987-06-26 Emulation system

Country Status (1)

Country Link
JP (1) JPS643745A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02129040U (en) * 1989-03-31 1990-10-24
US6553506B1 (en) 1998-03-31 2003-04-22 Seiko Epson Corporation Information processing device and electronic equipment
US7047443B2 (en) 1998-03-31 2006-05-16 Seiko Epson Corporation Microcomputer, electronic equipment and debugging system
US8041343B2 (en) 2006-02-23 2011-10-18 Qualcomm Incorporated Apparatus and methods for incentivized superdistribution of content

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02129040U (en) * 1989-03-31 1990-10-24
US6553506B1 (en) 1998-03-31 2003-04-22 Seiko Epson Corporation Information processing device and electronic equipment
WO2004102387A1 (en) * 1998-03-31 2004-11-25 Yoichi Hijikata Information processor and electronic device
US7047443B2 (en) 1998-03-31 2006-05-16 Seiko Epson Corporation Microcomputer, electronic equipment and debugging system
US7100086B1 (en) 1998-03-31 2006-08-29 Seiko Epson Corporation Microcomputer, electronic equipment and debugging system
US7114101B2 (en) 1998-03-31 2006-09-26 Seiko Epson Corporation Microcomputer, electronic equipment and debugging system
US8041343B2 (en) 2006-02-23 2011-10-18 Qualcomm Incorporated Apparatus and methods for incentivized superdistribution of content
US8447281B2 (en) 2006-02-23 2013-05-21 Qualcomm Incorporated Apparatus and methods for incentivized superdistribution of content
US9916595B2 (en) 2006-02-23 2018-03-13 Qualcomm Incorporated Apparatus and methods for incentivized superdistribution of content

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