JPS6437645A - Interface switching system - Google Patents
Interface switching systemInfo
- Publication number
- JPS6437645A JPS6437645A JP62193546A JP19354687A JPS6437645A JP S6437645 A JPS6437645 A JP S6437645A JP 62193546 A JP62193546 A JP 62193546A JP 19354687 A JP19354687 A JP 19354687A JP S6437645 A JPS6437645 A JP S6437645A
- Authority
- JP
- Japan
- Prior art keywords
- sdlc
- async
- interface
- bytes
- microcontroller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer And Data Communications (AREA)
Abstract
PURPOSE:To allow the titled system to correspond to both start-stop asynchronous (ASYNC) and SDLC systems only by replacing chips to a microcontroller by applying common hardware and software to a means similar to transmission control procedure. CONSTITUTION:When a MCS 51 is applied as a microcontroller 1, its families are 8051 and 8044, a difference based upon ASYNC or SDLC is applied to a serial port and also a difference is applied to the fact that an internal RAM is divided into 128 bytes for the ASYNC and 192 bytes for SDLC. Pins other than a serial port pin are used in common and the ROM external versions for both the ASYNC and SDLC are 8031 (1b interface) and 8344 (1a interface). At the time of ASYNC, A is used for transmission data and B is used for receiving data, and at the time of SDLC, A is used for both transmission and reception and B is not used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62193546A JPS6437645A (en) | 1987-08-01 | 1987-08-01 | Interface switching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62193546A JPS6437645A (en) | 1987-08-01 | 1987-08-01 | Interface switching system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6437645A true JPS6437645A (en) | 1989-02-08 |
Family
ID=16309866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62193546A Pending JPS6437645A (en) | 1987-08-01 | 1987-08-01 | Interface switching system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6437645A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8789868B1 (en) | 2013-03-06 | 2014-07-29 | Ford Global Technologies, Llc | Luggage retention system |
| US8801073B1 (en) | 2013-03-06 | 2014-08-12 | Ford Global Technologies, Llc | Luggage retention system |
-
1987
- 1987-08-01 JP JP62193546A patent/JPS6437645A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8789868B1 (en) | 2013-03-06 | 2014-07-29 | Ford Global Technologies, Llc | Luggage retention system |
| US8801073B1 (en) | 2013-03-06 | 2014-08-12 | Ford Global Technologies, Llc | Luggage retention system |
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