JPS643767A - Data transmission control unit in multi-cpu system - Google Patents

Data transmission control unit in multi-cpu system

Info

Publication number
JPS643767A
JPS643767A JP62158860A JP15886087A JPS643767A JP S643767 A JPS643767 A JP S643767A JP 62158860 A JP62158860 A JP 62158860A JP 15886087 A JP15886087 A JP 15886087A JP S643767 A JPS643767 A JP S643767A
Authority
JP
Japan
Prior art keywords
cpu
pull
reset
power
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62158860A
Other languages
Japanese (ja)
Inventor
Kazuhiro Araki
Kaoru Hashimoto
Shuji Maruta
Hiroichi Yamada
Yoshikazu Ikenoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Minolta Co Ltd
Original Assignee
Minolta Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minolta Co Ltd filed Critical Minolta Co Ltd
Priority to JP62158860A priority Critical patent/JPS643767A/en
Publication of JPS643767A publication Critical patent/JPS643767A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To continue the communication operation of the system even when the power of an optional slave CPU is interrupted or reset by providing a pull-down resistor or the like to a 3-state gate side of a control line and a pull-up resistor to an output port side. CONSTITUTION:Pull-down resistors 7-1-7-3 are provided to 3-state gates 6-1-6-3 of an enable line through which a signal is sent to the host CPU 1 from CPUs 2-1-2-3 and pull-up resistors 11-1-11-3 are provided to a slave CPU side. When a CPU 2-1, for example, is subject to power-off or reset, the control input of the gate 6-1 is brought into a low level by the resistor 7-1 and the gate 6-1 is opened. Thus, an enable signal to the CPU 2-1 is inputted to the CPU 2-2. That is, even when an optional slave CPU is subject to power-off or reset, a transmission enable signal is bypassed to the slave CPU of the next stage without any operation thereby keeping the communication operation of the system.
JP62158860A 1987-06-26 1987-06-26 Data transmission control unit in multi-cpu system Pending JPS643767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62158860A JPS643767A (en) 1987-06-26 1987-06-26 Data transmission control unit in multi-cpu system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62158860A JPS643767A (en) 1987-06-26 1987-06-26 Data transmission control unit in multi-cpu system

Publications (1)

Publication Number Publication Date
JPS643767A true JPS643767A (en) 1989-01-09

Family

ID=15680983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62158860A Pending JPS643767A (en) 1987-06-26 1987-06-26 Data transmission control unit in multi-cpu system

Country Status (1)

Country Link
JP (1) JPS643767A (en)

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