JPS6438862A - Program transfer system - Google Patents

Abstract

PURPOSE:To reduce software and hardware quantities by reading the program of a CPU 2 stored in the ROM of a CPU 1 with the CPU 1, preparing a common bus control signal and a writing signal, and transferring them to the RAM of the CPU 2. CONSTITUTION:Through the use of control signals 1a, 1b and 1c from the CPU 1 and the signal from an address bus 11, a decoder 9 decodes the buffer enable signals of the bus 11, namely, an enable signal 9b of a bus buffer IC 6, a buffer enable latch signal 9c of a bus transceiver to control a data bus 10, a writing signal 9d to a RAM 5 of CPUs 2 and 7, and a high-order address signal 9a of the RAM 5. The signal is outputted from the CPU 1 so as to output the signal 9d to the RAM 5, and the data read by the CPU 1 is written into the RAM 5. After the transfer of the program, when a signal 9e is outputted, data communication between the CPUs can be executed. Thus, the software and hardware quantities can be reduced.