JPS6441304A - Pll circuit for disk player - Google Patents

Abstract

PURPOSE:To simplify the constitution by setting the internal clock frequency via two-stage 1/2 frequencydividers at normal reproduction and setting the internal clock frequency via one-stage 1/2 frequency divider at double speed reproduction. CONSTITUTION:Since a changeover means 26 selects an output of the 2nd 1/2 frequency divider 25 at the normal reproduction, a 4.34MHz clock is obtained from the 1st frequency divider 27 and a phase comparator 22 compares the phase of the said clock and that of a reproduced EFM signal (4.34MHz). Thus, an internal clock in phase locked with the reproduced EFM signal is obtained from an output section 28. On the other hand, since the changeover means 26 selects the output of a voltage controlled oscillator 24 at the double speed reproduction, a 8.64MHz clock is obtained from the 1st frequency divider 27. Then the phase comparator 22 compares the phase between the clock and the reproduced EFM signal (8.64MHz). Thus, the internal clock for the normal reproduction and the internal clock for the double speed reproduction are obtained with simple constitution.