JPS6442732A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6442732A
JPS6442732A JP62198081A JP19808187A JPS6442732A JP S6442732 A JPS6442732 A JP S6442732A JP 62198081 A JP62198081 A JP 62198081A JP 19808187 A JP19808187 A JP 19808187A JP S6442732 A JPS6442732 A JP S6442732A
Authority
JP
Japan
Prior art keywords
instruction
floating point
point arithmetic
processing
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62198081A
Other languages
Japanese (ja)
Inventor
Michio Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62198081A priority Critical patent/JPS6442732A/en
Publication of JPS6442732A publication Critical patent/JPS6442732A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the accuracy of a branch prediction and to improve a processing speed of a branch instruction, by predicting a condition code of a result of processing a floating point addition/subtraction instruction and a floating point comparison instruction by using a fixed point arithmetic unit, in parallel with processing a floating point arithmetic instruction by a floating point arithmetic unit. CONSTITUTION:The titled processor is provided with a fixed point arithmetic unit and a floating point arithmetic unit in parallel, and constituted so as to process a fixed point arithmetic instruction and a floating point arithmetic instruction by the respective units. Also, this processor is provided with a means for predicting a condition code of a result of processing of the floating point arithmetic instruction, by using the fixed point arithmetic unit. In such a way, in the floating point arithmetic instruction, except the case when an underflow is generated in a result of processing of an addition/subtraction instruction and the result becomes '0', a condition code of a result of processing of a floating point addition/subtraction instruction, and a floating point comparison instruction can be exactly predicted, and a branch instruction which follows it up can be executed at a high speed.
JP62198081A 1987-08-10 1987-08-10 Information processor Pending JPS6442732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62198081A JPS6442732A (en) 1987-08-10 1987-08-10 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62198081A JPS6442732A (en) 1987-08-10 1987-08-10 Information processor

Publications (1)

Publication Number Publication Date
JPS6442732A true JPS6442732A (en) 1989-02-15

Family

ID=16385198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62198081A Pending JPS6442732A (en) 1987-08-10 1987-08-10 Information processor

Country Status (1)

Country Link
JP (1) JPS6442732A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011090623A (en) * 2009-10-26 2011-05-06 Nec Computertechno Ltd Floating-point retrieval calculation apparatus, method and program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011090623A (en) * 2009-10-26 2011-05-06 Nec Computertechno Ltd Floating-point retrieval calculation apparatus, method and program

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