JPS6443773A - Propagation delay testing method for logic circuit - Google Patents

Abstract

PURPOSE:To easily test a propagation delay by setting an optional flip-flop in an optional state directly from the outside. CONSTITUTION:An input variation signal is propagated on a path 117 to be tested and appears at a D entrance pin of the flip-flop 104. The variation at the D entrance is inputted to the flip-flop 104 unless there is no trouble of propagation delay on the path 117 to be tested. If, however, there is delay trouble, the flip-flop does not change its state. Here, the state of the flip-flop 104 is scanned out so as to decide the trouble of propagation delay on the path 117. Namely, the flip-flop 104 is selected with a scan-address pin 112 to obtain the state of the flip-flop 104 on the scan-out pin 116. This value shows there is no propagation delay on the tested path 117 when it is a signal value after the variation at the output terminal of the object path 117, but indicates the trouble of propagation delay on the object path 117, and consequently the propagation delay can be tested.