JPS6444475U - - Google Patents
Info
- Publication number
- JPS6444475U JPS6444475U JP13874587U JP13874587U JPS6444475U JP S6444475 U JPS6444475 U JP S6444475U JP 13874587 U JP13874587 U JP 13874587U JP 13874587 U JP13874587 U JP 13874587U JP S6444475 U JPS6444475 U JP S6444475U
- Authority
- JP
- Japan
- Prior art keywords
- output
- relay
- circuit
- input
- gate circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
Description
第１図はこの考案による実施例の構成図、第２
図は第１図のタイムチヤートの一例を示す図、第
３図はリレーを使用した構成図、第４図は第３図
のタイムチヤートの一例を示す図である。
１……ＦＦ、２……ＦＦ、３……一致検出回路
、４……一致検出回路、５……ゲート回路、６…
…リレー、７……リレー、８……リレー制御回路
、１１……バス、１２……測定器、１３……リレ
ー回路、１４……部品。
Figure 1 is a configuration diagram of an embodiment according to this invention, Figure 2
3 is a diagram showing an example of the time chart in FIG. 1, FIG. 3 is a block diagram using a relay, and FIG. 4 is a diagram showing an example of the time chart in FIG. 3. 1...FF, 2...FF, 3...Coincidence detection circuit, 4...Coincidence detection circuit, 5...Gate circuit, 6...
... Relay, 7 ... Relay, 8 ... Relay control circuit, 11 ... Bus, 12 ... Measuring instrument, 13 ... Relay circuit, 14 ... Parts.
Claims (1)
ＦＦ出力に接続されるリレーとで構成するリレー
制御回路において、 前記各ＦＦの入出力を比較する一致検出回路と
、 前記一致検出回路出力を並列入力とするゲート
回路とを備え、 前記ゲート回路出力があるときは前記リレーの
待ち時間Ｔを取り、前記ゲート回路出力がないと
きは前記リレーの待ち時間Ｔを取らないことを特
徴とするリレー制御回路。[Scope of Claim for Utility Model Registration] A relay control circuit comprising a plurality of FFs receiving setting data as input and a relay connected to each FF output, comprising: a coincidence detection circuit for comparing input and output of each FF; , and a gate circuit which receives the output of the coincidence detection circuit as a parallel input, and when there is an output of the gate circuit, the waiting time T of the relay is taken, and when there is no output of the gate circuit, the waiting time T of the relay is taken. A relay control circuit characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13874587U JPH0540457Y2 (en) | 1987-09-10 | 1987-09-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13874587U JPH0540457Y2 (en) | 1987-09-10 | 1987-09-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6444475U true JPS6444475U (en) | 1989-03-16 |
| JPH0540457Y2 JPH0540457Y2 (en) | 1993-10-14 |
Family
ID=31401369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13874587U Expired - Lifetime JPH0540457Y2 (en) | 1987-09-10 | 1987-09-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0540457Y2 (en) |
-
1987
- 1987-09-10 JP JP13874587U patent/JPH0540457Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0540457Y2 (en) | 1993-10-14 |
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