JPS6444632A - Data controller in rds receiver - Google Patents

Data controller in rds receiver

Info

Publication number
JPS6444632A
JPS6444632A JP20243187A JP20243187A JPS6444632A JP S6444632 A JPS6444632 A JP S6444632A JP 20243187 A JP20243187 A JP 20243187A JP 20243187 A JP20243187 A JP 20243187A JP S6444632 A JPS6444632 A JP S6444632A
Authority
JP
Japan
Prior art keywords
multipath
data
fetching
detection output
multipath disturbance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20243187A
Other languages
Japanese (ja)
Inventor
Koichi Ryu
Toshito Ichikawa
Junichi Nishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP20243187A priority Critical patent/JPS6444632A/en
Publication of JPS6444632A publication Critical patent/JPS6444632A/en
Pending legal-status Critical Current

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  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To prevent the fetching of erroneous correction data which is apt to occur due to the degradation in reception state, by detecting the multipath disturbance of a reception broadcast wave and inhibiting the fetching of demodulated data during the generation of this detection output. CONSTITUTION:The detection output of a multipath detecting circuit 18 which detects the multipath disturbance of the reception broadcast wave based on the FM detection output is supplied to a controller 14, and a switch circuit 17 is opened while the multipath disturbance occurs. Since the supply of demodulated data and a clock to a group and block synchronizing and error detecting circuit 12 is stopped then, data is inhibited from being fetched to the controller 14 while the multipath disturbance occurs. Thus, the fetching of erroneous data is prevented in case of erroneous error correction due to the degradation in reception state accompanied with the occurrence of the multipath disturbance.
JP20243187A 1987-08-13 1987-08-13 Data controller in rds receiver Pending JPS6444632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20243187A JPS6444632A (en) 1987-08-13 1987-08-13 Data controller in rds receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20243187A JPS6444632A (en) 1987-08-13 1987-08-13 Data controller in rds receiver

Publications (1)

Publication Number Publication Date
JPS6444632A true JPS6444632A (en) 1989-02-17

Family

ID=16457403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20243187A Pending JPS6444632A (en) 1987-08-13 1987-08-13 Data controller in rds receiver

Country Status (1)

Country Link
JP (1) JPS6444632A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065452A (en) * 1988-06-18 1991-11-12 Robert Bosch Gmbh Digital traffic news evaluation method
US5181208A (en) * 1988-07-18 1993-01-19 Robert Bosch Gmbh Computation-conserving traffic data transmission method and apparatus
US5182754A (en) * 1989-02-09 1993-01-26 Nec Corporation Microprocessor having improved functional redundancy monitor mode arrangement

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065452A (en) * 1988-06-18 1991-11-12 Robert Bosch Gmbh Digital traffic news evaluation method
US5181208A (en) * 1988-07-18 1993-01-19 Robert Bosch Gmbh Computation-conserving traffic data transmission method and apparatus
US5182754A (en) * 1989-02-09 1993-01-26 Nec Corporation Microprocessor having improved functional redundancy monitor mode arrangement

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