JPS6446104A - Checking device for double application of output instruction - Google Patents

Checking device for double application of output instruction

Info

Publication number
JPS6446104A
JPS6446104A JP62203008A JP20300887A JPS6446104A JP S6446104 A JPS6446104 A JP S6446104A JP 62203008 A JP62203008 A JP 62203008A JP 20300887 A JP20300887 A JP 20300887A JP S6446104 A JPS6446104 A JP S6446104A
Authority
JP
Japan
Prior art keywords
output instruction
selecting
circuit
instruction
coincident
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62203008A
Other languages
Japanese (ja)
Inventor
Susumu Matsumoto
Susumu Saito
Tetsuo Tsunoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP62203008A priority Critical patent/JPS6446104A/en
Publication of JPS6446104A publication Critical patent/JPS6446104A/en
Pending legal-status Critical Current

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Landscapes

  • Programmable Controllers (AREA)
  • Testing And Monitoring For Control Systems (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To shorten the checking time for double application of an output instruction by using an output instruction detecting circuit and an output instruction selecting circuit which decides whether or not an output instruction is coincident with the selecting conditions shown by a selecting condition table. CONSTITUTION:An output instruction detecting circuit 3 detects that the program instruction outputted from a program memory 2 is equal to an output instruction and delivers a signal showing the presence of the output instruction to a signal line (c). An output instruction selecting circuit 4 receives said signal via the line (c) and checks whether this signal is coincident or not with the selecting conditions shown by a selecting condition table 5. Then an output instruction coincident with the selecting conditions is outputted to a bus (g). In such a case, the table 5 delivers a number pointed by a table pointer 5' to the circuit 4 as the selecting conditions. The circuit 4 selects an input instruction that secures the coincidence between said received number and the lowest level number of the pointed address of the output instruction. In such a way, the reading frequency of the output instruction is decreased and the checking time is shortened for double application of the output instruction.
JP62203008A 1987-08-17 1987-08-17 Checking device for double application of output instruction Pending JPS6446104A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62203008A JPS6446104A (en) 1987-08-17 1987-08-17 Checking device for double application of output instruction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62203008A JPS6446104A (en) 1987-08-17 1987-08-17 Checking device for double application of output instruction

Publications (1)

Publication Number Publication Date
JPS6446104A true JPS6446104A (en) 1989-02-20

Family

ID=16466805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62203008A Pending JPS6446104A (en) 1987-08-17 1987-08-17 Checking device for double application of output instruction

Country Status (1)

Country Link
JP (1) JPS6446104A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55166757A (en) * 1979-06-15 1980-12-26 Sharp Corp Check unit for overlapping use of output instruction
JPS56153445A (en) * 1980-04-28 1981-11-27 Fujitsu Ltd Data sorting system by assignment of permissible error range
JPS59121537A (en) * 1982-12-28 1984-07-13 Nec Corp Bit pattern collating circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55166757A (en) * 1979-06-15 1980-12-26 Sharp Corp Check unit for overlapping use of output instruction
JPS56153445A (en) * 1980-04-28 1981-11-27 Fujitsu Ltd Data sorting system by assignment of permissible error range
JPS59121537A (en) * 1982-12-28 1984-07-13 Nec Corp Bit pattern collating circuit

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