JPS644697B2 - - Google Patents

Abstract

PURPOSE:To reduce the current in the queuing mode for a signal receiver containing a phase synchronizing oscillator, by controlling the oscillating frequency with the DC output voltage of a discriminator of the receiver in the queuing mode and cutting off the power supply of the circuit in a phase synchronizing loop. CONSTITUTION:In the calling mode, a power supply switch 23 of a signal reciever and the switches 7 and 16 of a power supply at the phase synchronizing part are closed with a switch 15 opened. The oscillating frequency of a voltage control oscillator 1 which is divided by a frequency divider 2 is compared with the output of a quartz oscillator 5 which is divided by a frequency divider 4 through a phase wave detector 3. The output of the comparison controls the oscillator 1 via an adder 9. In the queuing mode, the switches 16 and 7 are opened with the switch 15 closed. Then the DC component separated by a low pass filter 13 among the output of a discriminator 12 is amplified by an amplifier 14 and supplied to the adder 9 via the switch 15 to be added with the terminal voltage of a capacitor 8. Thus a synchronizing loop is formed to control the oscillator 1. In the detection mode of a call signal or in case the frequency deviation is large, the switch 15 is opened with the switches 7 and 16 closed respectively by a control circuit 21.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a receiver mainly used as a mobile station such as a car telephone or a wireless telephone.

2. Description of the Related Art In general, mobile phones and the like must constantly monitor the current location of a mobile station, so a base station always transmits a predetermined radio wave. When a mobile station receives the radio waves, it must inform the base station of its own location, and if it receives a call from the base station, it must immediately respond to the call, so at least the receiver's power supply is always on, even in standby mode. It is configured so that it must be turned on.

Problems to be Solved by the Invention Therefore, this type of receiver consumes a considerable amount of power even in standby mode, and mobile stations that use batteries as a power source have the problem that the talkable time is severely limited. .

In particular, when a phase-locked loop is used as the local oscillator circuit, the power consumption in the loop becomes extremely large, and there is a problem in that the time during which talk can be made is further significantly restricted.

The present invention eliminates the above-mentioned conventional drawbacks, and aims to provide an excellent receiver that has a simple configuration and can significantly reduce power consumption in a standby state.

Means for Solving the Problems The present invention uses a phase-locked loop as a local oscillation circuit, turns off the loop during standby, and automatically eliminates the subsequent drift of the voltage controlled oscillator using the DC output of the disc discriminator of the receiver. The structure is designed to correct the situation.

Therefore, according to the present invention, while using a phase-locked loop as a local oscillation circuit, the loop is turned off during standby, so power consumption during standby is not so large, and it can be used as a power source. Even when using a battery, it has the effect of allowing a sufficient amount of talk time.

Embodiment FIG. 1 is a block diagram of an embodiment of a receiver according to the present invention. In Figure 1, 1 is a voltage controlled oscillator (hereinafter referred to as VCO) that acts as a local oscillator circuit.
), 2 is a variable frequency divider, 3 is a phase detector that receives the output of the variable frequency divider 2 and the output of the fixed frequency divider 4, 5 is a crystal oscillator, 6 is a low-pass filter (hereinafter referred to as LPF), etc. A loop filter consisting of
7 is a first switch that turns on and off the output of the loop filter 6; 8 is a capacitor; 9 is an adder;
0 is the high frequency signal received by the receiving antenna and the
A mixing circuit for mixing the output of the VCO 1, 11 an intermediate frequency amplifier, 12 a discriminator, 13 a low pass filter (hereinafter referred to as LPF), 14 a DC amplifier, 15 turning on the output of the DC amplifier 14,
16 is a third switch that turns on and off the power of the frequency dividers 2, 4, phase detector 3, etc. that constitute the phase-locked loop; 17 is connected to the rear stage of the discriminator 12; 18 is a detection circuit that detects when the received high-frequency signal is abnormally small; 19 is a detection circuit that detects a received frequency shift based on the output of the DC amplifier 14; 20 is a low frequency amplifier that amplifies the output of the discriminator 12; 21 receives the outputs of the sign determination circuit 17, the detection circuit 18, the reception frequency deviation detection circuit 19, etc.; A control circuit controls the second and third switches 7, 15, and 16, 22 is a receiver, and 23 is a receiver power switch.

In the above embodiment, it is assumed that the power switch 23 is now turned on and the receiver is in a talking state. In the call state, the control circuit 21 controls the first and third
switches 7 and 16 are on, second switch 15
is in the off state. Therefore, in this case, the power supply voltage is applied to the frequency dividers 2, 4, phase detector 3, etc., and these circuits are in an operating state.
That is, the output of the VCO 1 is applied to the mixing circuit 10 and also to the frequency divider 2, where the frequency is divided. The signal frequency-divided by the frequency divider 2 is compared with the signal frequency-divided by the frequency divider 4 by the phase detector 2. The error signal is applied to the VCO 1 via the loop filter 6, the first switch 7, and the adder 9, thereby forming a phase-locked loop as a whole. Therefore, the oscillation frequency of VCO1 is locked by this loop and becomes extremely stable.

And VCO1 stabilized in this way
The output is supplied to the mixer 10, mixed with the high frequency signal ( _IN ) received by the receiving antenna, and converted into an intermediate frequency signal ( _VCO - _IN ). The intermediate frequency signal is amplified by an intermediate frequency amplifier 11, FM detected by a discriminator 12, and guided to a receiver 22 via a control circuit 21.

Next, in the standby state, the control circuit 21 turns off the first and third switches 7 and 16, and turns on the second switch 15. Therefore, in this case, the power to the frequency dividers 2, 4, phase detector 3, etc. that make up the phase periodic loop is turned off, and at the same time, the above loop is "cut off", and the power consumption by the above loop is reduced. almost disappears. In this case, from the output of the disc discriminator 12, the LPF1
3 and amplified by the DC amplifier 14 is applied to the adder 9 via the second switch 15, where the terminal voltage of the capacitor 8 is added and applied to the VCO 1. , automatic frequency control (AFC) is applied in this loop.

Therefore, the oscillation frequency of VCO1 does not change much from the call state with the phase-locked loop "closed",
Radio waves from the base station can be sufficiently received.

That is, according to the above embodiment, the voltage charged in the capacitor 8 in the talking state is applied to the VCO 1 via the adder 9 even in the standby state, and therefore, the voltage charged in the capacitor 8 in the talking state is applied to the VCO 1 through the adder 9. Even when switching to , the oscillation frequency of VCO 1 does not change significantly and the switching can be performed smoothly. Then, when the charge accumulated in the capacitor 8 in the standby state gradually discharges and its terminal voltage decreases, the output of the DC amplifier 14 is added to the terminal voltage of the capacitor 8 by the AFC loop. The voltage applied to the VCO 1 is finally controlled to be the same as that in the talking state, and the oscillation frequency of the VCO 1 is automatically maintained at a stable value by the AFC loop.

If the terminal voltage of the capacitor 8 drops to a range beyond which the AFC loop cannot be controlled, the output of the DC amplifier 14 provided to compensate for it will naturally become larger than a predetermined value.

Therefore, in this case, it is detected by the frequency deviation detection circuit 19, and the control circuit 21 turns on the first and third switches 7 and 16, and turns off the second switch 15. Therefore, in this state, the VCO 1 is locked again in the phase locked loop, and the terminal voltage of the capacitor 8 also returns to its original state. Therefore, to continue to maintain the standby state, the control circuit 21 may be used again to turn off the first and third switches 7 and 16 and turn on the second switch 15. In this way, even if the terminal voltage of the capacitor 8 drops to a range that is beyond the control of the AFC loop, it can be easily corrected and corrected to an accurate value.

Further, according to the above embodiment, the detection circuit 18 detects when the received signal becomes abnormally small.
When a call is received from a base station or a base station, a code determination circuit 17 is provided to detect the call signal, etc., and the output thereof is applied to the control circuit 21, so that the signal is received. When the signal becomes abnormally small or when a call is received from the base station, the control circuit 21 switches the first and third switches 7, 7, By turning on the second switch 16 and turning off the second switch 15, the oscillation frequency of the VCO 1 can be corrected to an accurate value by the phase-locked loop.

FIG. 2 shows the structure of another embodiment of the portion surrounded by dotted lines in FIG. 1.

In FIG. 2, 24 is an A/D converter;
5 is a memory, 26 is a D/A converter, 27 is an adder, and 28 and 29 are switches.

In the call state, the switch 28
6 side, and the VCO is connected in a phase-locked loop.
1 is frequency controlled. And at the same time
The output of the LPF 6 is digitally encoded by the A/D converter 24 at regular intervals and stored in the memory 25. When the standby state is reached, the switch 28 is turned on to the adder 27 side, stopping the operation of the A/D converter 24 and turning off the switch 29.
The contents of the memory 25 are maintained in the state immediately before entering the standby state. Then, the contents of the memory 25 are
The A converter 26 converts the voltage into a DC value, which is added to the DC voltage value output from the discriminator 12 by an adder 27, thereby controlling the VCO 1. In this way, capacitor 18
Although the accuracy is inferior to that of holding the voltage at
It has the advantage of being able to hold this voltage value for a long period of time.

Effects of the Invention As explained above in conjunction with the embodiments, according to the present invention, in a call state, the phase-locked loop allows
The above phase-locked loop is constructed by controlling the oscillation frequency of the voltage variable frequency oscillator with the accuracy of the reference crystal oscillator, and in the standby state, controlling the oscillation frequency of the voltage variable frequency oscillator with the DC output voltage of the discriminator. The power to the frequency divider, reference crystal oscillator, and frequency phase comparator can be turned off, reducing the current during standby.
For portable radios with long standby reception times,
Its usage time can be significantly extended, and its industrial value is great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of a receiver according to the present invention, and FIG. 2 is a block diagram of main parts of another embodiment. 1...VCO, 5...Crystal oscillator, 12...Discriminator, 8...Capacitor, 7...First switch, 15...Second switch, 16...
...Third switch, 9...Adder.

Claims (1)

[Claims] 1. An adder is provided before the voltage controlled oscillator that constitutes the local oscillation circuit, and the phase comparison voltage obtained by comparing the output of the voltage controlled oscillator and the reference frequency is held at one input terminal of the adder. and a DC output voltage of a discriminator for FM detecting an intermediate frequency signal obtained using the output of the local oscillation circuit is applied to the other input terminal of the adder. The output is configured to control the oscillation frequency of the local oscillation circuit, and the DC output voltage of the discriminator is not applied to the other input terminal of the adder during a call to each stage before the adder. west,
Selecting means applies the DC output voltage of the discriminator to the other input terminal of the adder only during standby, and disconnects a phase locked loop including a phase detector for obtaining the phase comparison voltage during standby. A receiver equipped with a means for