JPS6447982A - Multi-channel gps receiver - Google Patents

Multi-channel gps receiver

Info

Publication number
JPS6447982A
JPS6447982A JP20444587A JP20444587A JPS6447982A JP S6447982 A JPS6447982 A JP S6447982A JP 20444587 A JP20444587 A JP 20444587A JP 20444587 A JP20444587 A JP 20444587A JP S6447982 A JPS6447982 A JP S6447982A
Authority
JP
Japan
Prior art keywords
processors
signal
clock
channels
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20444587A
Other languages
Japanese (ja)
Inventor
Masanobu Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20444587A priority Critical patent/JPS6447982A/en
Publication of JPS6447982A publication Critical patent/JPS6447982A/en
Pending legal-status Critical Current

Links

Landscapes

  • Radio Relay Systems (AREA)
  • Position Fixing By Use Of Radio Waves (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To enable the measurement in the order of below microsecond, by using a processor for high signal processing at channels while a clock, an interrupt signal and a reset signal of processors at the channels are used in common. CONSTITUTION:Receiving circuits 121-12n at channels are provided with processors b1-bn for high speed signal processing. A clock CK and an interrupt signal 1 generated with a timing control circuit 14 are supplied in common to the processors b1-bn. A reset signal R generated with a host CMU 15 is supplied in common. In other words, the processors b1-bn are reset simultaneously by the signal R from the CPU 15 to start operation. Thereafter as long as there is no alteration in a processor processing step by satellite-received information with the use of the clock CK, a deviation of measured values at the receiving time in the results of a signal processing of the processors b1-bn only gives a working time deviation thereby enabling calculation of the results of a measurement processing sufficiently in the order of below microsecond.
JP20444587A 1987-08-18 1987-08-18 Multi-channel gps receiver Pending JPS6447982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20444587A JPS6447982A (en) 1987-08-18 1987-08-18 Multi-channel gps receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20444587A JPS6447982A (en) 1987-08-18 1987-08-18 Multi-channel gps receiver

Publications (1)

Publication Number Publication Date
JPS6447982A true JPS6447982A (en) 1989-02-22

Family

ID=16490645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20444587A Pending JPS6447982A (en) 1987-08-18 1987-08-18 Multi-channel gps receiver

Country Status (1)

Country Link
JP (1) JPS6447982A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019155703A1 (en) * 2018-02-09 2019-08-15 ソニーセミコンダクタソリューションズ株式会社 Satellite positioning signal reception device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019155703A1 (en) * 2018-02-09 2019-08-15 ソニーセミコンダクタソリューションズ株式会社 Satellite positioning signal reception device
JPWO2019155703A1 (en) * 2018-02-09 2021-01-28 ソニーセミコンダクタソリューションズ株式会社 Satellite positioning signal receiver
US11841445B2 (en) 2018-02-09 2023-12-12 Sony Semiconductor Solutions Corporation Satellite positioning signal receiving device

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