JPS6448158A - Direct memory access control circuit - Google Patents

Direct memory access control circuit

Info

Publication number
JPS6448158A
JPS6448158A JP20407687A JP20407687A JPS6448158A JP S6448158 A JPS6448158 A JP S6448158A JP 20407687 A JP20407687 A JP 20407687A JP 20407687 A JP20407687 A JP 20407687A JP S6448158 A JPS6448158 A JP S6448158A
Authority
JP
Japan
Prior art keywords
transfer
latch
dma
control part
memory address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20407687A
Other languages
Japanese (ja)
Other versions
JP2563807B2 (en
Inventor
Tsutomu Odawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62204076A priority Critical patent/JP2563807B2/en
Publication of JPS6448158A publication Critical patent/JPS6448158A/en
Application granted granted Critical
Publication of JP2563807B2 publication Critical patent/JP2563807B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To load saved data in the same order as input by providing a latch/ transfer circuit, a latch/transfer control part, and an I/O device control part to fix the memory address progress direction for direct memory access (DMA) transfer. CONSTITUTION:Two-way latch/transfer circuits 19 and 20 which latch or transfer 8-bit data connected to upper bits and lower bits of a 16-bit data bus, a latch/trasfer control part 31 which is provided with a register 23 in which the data transfer direction for DMA transfer is stored and a register 24 in which the memory address progress direction is stored and controls latch/transfer circuits 19 and 20, and an I/O device control part 14 which outputs a signal required for DMA to a DMA 5 and outputs a read signal or a write signal to an I/O device 7 are provided. Consequently, the memory address progress direction for DMA transfer at the time of saving and loading is fixed and data saved in the I/O device is loaded to the memory in the same order as input to improve the operability.
JP62204076A 1987-08-19 1987-08-19 Direct memory access control circuit Expired - Lifetime JP2563807B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62204076A JP2563807B2 (en) 1987-08-19 1987-08-19 Direct memory access control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62204076A JP2563807B2 (en) 1987-08-19 1987-08-19 Direct memory access control circuit

Publications (2)

Publication Number Publication Date
JPS6448158A true JPS6448158A (en) 1989-02-22
JP2563807B2 JP2563807B2 (en) 1996-12-18

Family

ID=16484376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62204076A Expired - Lifetime JP2563807B2 (en) 1987-08-19 1987-08-19 Direct memory access control circuit

Country Status (1)

Country Link
JP (1) JP2563807B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118133A (en) * 1980-02-25 1981-09-17 Nippon Telegr & Teleph Corp <Ntt> Direct memory access circuit
JPS60211557A (en) * 1984-04-06 1985-10-23 Seiko Epson Corp Direct memory access control circuit
JPS61150055A (en) * 1984-12-25 1986-07-08 Panafacom Ltd Dma data transfer system
JPS61175750A (en) * 1985-01-30 1986-08-07 Nec Corp Microprocessor system with dma function

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118133A (en) * 1980-02-25 1981-09-17 Nippon Telegr & Teleph Corp <Ntt> Direct memory access circuit
JPS60211557A (en) * 1984-04-06 1985-10-23 Seiko Epson Corp Direct memory access control circuit
JPS61150055A (en) * 1984-12-25 1986-07-08 Panafacom Ltd Dma data transfer system
JPS61175750A (en) * 1985-01-30 1986-08-07 Nec Corp Microprocessor system with dma function

Also Published As

Publication number Publication date
JP2563807B2 (en) 1996-12-18

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