JPS6448163A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS6448163A
JPS6448163A JP20544387A JP20544387A JPS6448163A JP S6448163 A JPS6448163 A JP S6448163A JP 20544387 A JP20544387 A JP 20544387A JP 20544387 A JP20544387 A JP 20544387A JP S6448163 A JPS6448163 A JP S6448163A
Authority
JP
Japan
Prior art keywords
processor
internal register
another
data
erg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20544387A
Other languages
Japanese (ja)
Inventor
Taketoshi Yasumuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20544387A priority Critical patent/JPS6448163A/en
Publication of JPS6448163A publication Critical patent/JPS6448163A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To eliminate a need of a shared memory and to quickly transfer data in accordance with simple procedures by transferring data from one processor to another by direct transfer from an internal register of one processor to that of another. CONSTITUTION:A two-port internal register (ERG) is provided which has one port connected to the internal bus of its own processor and has the other port connected to a processor interface (MPIF) and is so constituted that this ERG can be accessed from another processor, and a semaphore bit (SB) is provided in the ERG to synchronize the external access to the internal register. Each processor refers to the SB to discriminate whether access to the internal register in another processor is possible or not, and data is directly transferred between respective internal register if the SB indicates that this access is possible. Thus, a shared memory is unnecessary and data is quickly transferred in accordance with simple procedures.
JP20544387A 1987-08-19 1987-08-19 Multiprocessor system Pending JPS6448163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20544387A JPS6448163A (en) 1987-08-19 1987-08-19 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20544387A JPS6448163A (en) 1987-08-19 1987-08-19 Multiprocessor system

Publications (1)

Publication Number Publication Date
JPS6448163A true JPS6448163A (en) 1989-02-22

Family

ID=16506967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20544387A Pending JPS6448163A (en) 1987-08-19 1987-08-19 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPS6448163A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997041514A1 (en) * 1996-04-30 1997-11-06 3Com Corporation Qualified burst buffer
WO2012029111A1 (en) 2010-08-30 2012-03-08 富士通株式会社 Multi-core processor system, synchronisation control system, synchronisation control device, information generation method, and information generation programme

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997041514A1 (en) * 1996-04-30 1997-11-06 3Com Corporation Qualified burst buffer
WO2012029111A1 (en) 2010-08-30 2012-03-08 富士通株式会社 Multi-core processor system, synchronisation control system, synchronisation control device, information generation method, and information generation programme
JP5488697B2 (en) * 2010-08-30 2014-05-14 富士通株式会社 Multi-core processor system, synchronization control method, and synchronization control program
US9367311B2 (en) 2010-08-30 2016-06-14 Fujitsu Limited Multi-core processor system, synchronization control system, synchronization control apparatus, information generating method, and computer product

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