JPS6448165A - Multiple cpu control system with cpu only for special processing - Google Patents
Multiple cpu control system with cpu only for special processingInfo
- Publication number
- JPS6448165A JPS6448165A JP20562887A JP20562887A JPS6448165A JP S6448165 A JPS6448165 A JP S6448165A JP 20562887 A JP20562887 A JP 20562887A JP 20562887 A JP20562887 A JP 20562887A JP S6448165 A JPS6448165 A JP S6448165A
- Authority
- JP
- Japan
- Prior art keywords
- processing
- cpu
- special processing
- special
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 abstract 2
- 238000001514 detection method Methods 0.000 abstract 1
Landscapes
- Advance Control (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To quickly perform the information processing including a special processing by detecting a special processing instruction from a general processing program and performing the processing of the special processing instruction by a CPU only for special processing and receiving the processing result to perform the processing by a CPU for general processing. CONSTITUTION:Execution of the special processing instruction in the general processing program is detected by a special processing instruction detecting means 21 of a special processing instruction control means 2. By this detection, execution of this special processing instruction is transferred to a CPU 1 only for special processing provided with a program only for special processing. The end and the result of the processing in the CPU 1 only for special processing are received, the the processing result is transferred to the CPU for general processing, and execution of the general processing program is continued to perform the information processing. Thus, the program including the special processing is quickly operated under multiple programs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20562887A JPS6448165A (en) | 1987-08-19 | 1987-08-19 | Multiple cpu control system with cpu only for special processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20562887A JPS6448165A (en) | 1987-08-19 | 1987-08-19 | Multiple cpu control system with cpu only for special processing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6448165A true JPS6448165A (en) | 1989-02-22 |
Family
ID=16510040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20562887A Pending JPS6448165A (en) | 1987-08-19 | 1987-08-19 | Multiple cpu control system with cpu only for special processing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6448165A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04109062A (en) * | 1990-08-28 | 1992-04-10 | Hitachi Ltd | Abnormal combustion detection device for internal combustion engine and torque control device for internal combustion engine |
| JP2008090849A (en) * | 1994-10-27 | 2008-04-17 | Intarsia Software Llc | Data copyright management apparatus |
-
1987
- 1987-08-19 JP JP20562887A patent/JPS6448165A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04109062A (en) * | 1990-08-28 | 1992-04-10 | Hitachi Ltd | Abnormal combustion detection device for internal combustion engine and torque control device for internal combustion engine |
| JP2008090849A (en) * | 1994-10-27 | 2008-04-17 | Intarsia Software Llc | Data copyright management apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0378425A3 (en) | Branch instruction execution apparatus | |
| TW358919B (en) | System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture | |
| EP0340453A3 (en) | Instruction handling sequence control system | |
| EP0377994A3 (en) | Apparatus for performing floating point arithmetic operations | |
| TW332266B (en) | Execution of data processing instructions | |
| TW260765B (en) | ||
| EP0790556A3 (en) | Emulating a delayed exception on a digital computer having a corresponding precise exception mechanism | |
| EP0402856A3 (en) | Instruction execution control system | |
| EP0130381A3 (en) | Mechanism for implementing one machine cycle executable branch-on-any-bit-in-any-register instructions in a primitive instruction set computing system | |
| EP0247380A3 (en) | Data display-controlling device for data-processing apparatus | |
| JPS5340244A (en) | On-line system constitution system | |
| JPS6448165A (en) | Multiple cpu control system with cpu only for special processing | |
| JPS5614932A (en) | Automatic diagnostic system | |
| EP0319132A3 (en) | Interrupt handling in a parallel data processing | |
| EP0325226A3 (en) | Information processing apparatus and method | |
| JPS5471537A (en) | Failure processing system for multiprocessor | |
| JPS5388545A (en) | Processing system for vector order | |
| JPS56147246A (en) | Program control device | |
| JPS647844A (en) | Error detecting system for external set value | |
| JPS53114628A (en) | Io interruption control system | |
| JPS6485497A (en) | Plant supervisory equipment | |
| JPS53126836A (en) | Data processor | |
| JPS6435636A (en) | Evaluating system for test program for information processor | |
| JPS54534A (en) | Advance control system of instruction in information processor | |
| JPS5296835A (en) | Error detection method |